diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2012-12-02 04:49:53 +0000 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2012-12-06 14:30:39 -0800 |
| commit | 17de114f9f925eb740d813476fe486154fa8df91 (patch) | |
| tree | d4e34e440f5afd9eac1083e267d2f23c3277ddda /arch/x86/cpu | |
| parent | 98568f0fa96bca77382ec6fdf06852ada559c2bf (diff) | |
x86: Clean up MTRR 7 right before jumping to the kernel
This cleans up the rom caching optimization implemented in coreboot (and
needed throughout U-Boot runtime).
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/cpu')
| -rw-r--r-- | arch/x86/cpu/coreboot/coreboot.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index b942a3e3e2e..f2628009177 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -26,6 +26,8 @@ #include <asm/u-boot-x86.h> #include <flash.h> #include <netdev.h> +#include <asm/msr.h> +#include <asm/cache.h> #include <asm/arch-coreboot/tables.h> #include <asm/arch-coreboot/sysinfo.h> #include <asm/arch/timestamp.h> @@ -89,3 +91,19 @@ int board_eth_init(bd_t *bis) void setup_pcat_compatibility() { } + +#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) +#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) + +int board_final_cleanup(void) +{ + /* Un-cache the ROM so the kernel has one + * more MTRR available. + */ + disable_caches(); + wrmsrl(MTRRphysBase_MSR(7), 0); + wrmsrl(MTRRphysMask_MSR(7), 0); + enable_caches(); + + return 0; +} |