diff options
author | Bin Meng <bmeng.cn@gmail.com> | 2017-08-15 22:38:31 -0700 |
---|---|---|
committer | Bin Meng <bmeng.cn@gmail.com> | 2017-08-24 11:00:47 +0800 |
commit | 1e6ebee667da47fd3a87839a239a7574c66f5659 (patch) | |
tree | eb5774d7d1cc4db39b78c015eb5733f8807de07f /arch/x86/Kconfig | |
parent | b42711f90c66d683b808cd78d9748ab38407413f (diff) |
x86: fsp: Configure SPI opcode registers before SPI is locked down
Some Intel FSP (like Braswell) does SPI lock-down during the call
to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
it's bootloader's responsibility to configure the SPI controller's
opcode registers properly otherwise SPI controller driver doesn't
know how to communicate with the SPI flash device.
This introduces a Kconfig option CONFIG_FSP_LOCKDOWN_SPI for such
FSPs. When it is on, U-Boot will configure the SPI opcode registers
before the lock-down.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/x86/Kconfig')
-rw-r--r-- | arch/x86/Kconfig | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index c26710b484c..53730829571 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -401,6 +401,15 @@ config FSP_BROKEN_HOB do not overwrite the important boot service data which is used by FSP, otherwise the subsequent call to fsp_notify() will fail. +config FSP_LOCKDOWN_SPI + bool + depends on HAVE_FSP + help + Some Intel FSP (like Braswell) does SPI lock-down during the call + to fsp_notify(INIT_PHASE_BOOT). This option should be turned on + for such FSP and U-Boot will configure the SPI opcode registers + before the lock-down. + config ENABLE_MRC_CACHE bool "Enable MRC cache" depends on !EFI && !SYS_COREBOOT |