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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2023-02-23 11:25:52 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2023-02-23 12:28:47 +0100 |
| commit | 1004c8e6ee12f2f245c34441ab98887c54ca123e (patch) | |
| tree | dba9b5a36d10a358f86ad83b28a30440baccf726 /arch/riscv | |
| parent | 01c6b5880dda2d2875995e129d57fa849174b5ed (diff) | |
arm: dts: k3-am625-verdin-lpddr4-1600MTs: update to sysconfig v0.09.05
Update LPDDR4 RAM timings to what the online AM62x SysConfig DDR
Subsystem Register Configuration Tool v0.09.05 generates. From its
README:
v9.04:
-changed wrlvl_delay_early_threshold=0x100 to allow write leveling
to complete successfully for wider array of layouts
-add cmm output
-LPDDR4: phy_rddqs_latency_adjust changed to 0 default
recommendation (this value gets optimized during training)
-LPDDR4: optimized training loops to support 1 operating frequency
-LPDDR4/DDR4: optimized IO calibration configuration based on
operating frequency
-LPDDR4/DDR4: optimized internal calibration clock based on
operating frequency
-LPDDR4: changed default MR22 ODTE-CS=1
-LPDDR4: changed rx_ctle_cs default to No Boost
-AM62x dual rank support
-updated to use sysconfig v1.15
-public release for AM62A LPDDR4 support
v9.05:
-cleaned up supported frequencies
Upstream-Status: Pending
Initial U-Boot to be used for bring-up and validation of the V1.0
design, we'll decide on the step forward to mainline this once the
bring-up and validation will be done.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'arch/riscv')
0 files changed, 0 insertions, 0 deletions