diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2021-06-04 13:51:12 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2021-06-17 09:39:08 +0800 |
| commit | 048aff6d2621df2654dce6f833a2cf843358486a (patch) | |
| tree | daf0055c9f961f0a3dad8f9139e328364307bf10 /arch/riscv | |
| parent | f050dd2b26abb4b107c3cdf7a5f5c420a9e1d4b6 (diff) | |
riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
All the device nodes that refer to plic0 as their interrupt parent
have 2 cells encoded in their interrupts property, but plic0 only
provides 1 cell in #interrupt-cells which is incorrect.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/dts/ae350_32.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index 0917b83108..70576846f2 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -135,7 +135,7 @@ plic0: interrupt-controller@e4000000 { compatible = "riscv,plic0"; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupt-controller; reg = <0xe4000000 0x2000000>; riscv,ndev=<71>; |