diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2018-12-12 06:12:43 -0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2018-12-18 09:56:27 +0800 |
| commit | 10753ef8fd14dfe1d41ec253966569de19463adc (patch) | |
| tree | 172dde763aa535bab9a515bcb90de35da1196e57 /arch/riscv | |
| parent | 496262cca63f25408c6715b39cea1747e8ce9b59 (diff) | |
riscv: Return to previous privilege level after trap handling
At present the trap handler returns to hardcoded M-mode/S-mode.
Change to returning to previous privilege level instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/mtrap.S | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S index da307e4273..407ecfa9c0 100644 --- a/arch/riscv/cpu/mtrap.S +++ b/arch/riscv/cpu/mtrap.S @@ -68,14 +68,6 @@ trap_entry: jal handle_trap csrw MODE_PREFIX(epc), a0 -#ifdef CONFIG_RISCV_SMODE - /* Remain in S-mode after sret */ - li t0, SSTATUS_SPP -#else - /* Remain in M-mode after mret */ - li t0, MSTATUS_MPP -#endif - csrs MODE_PREFIX(status), t0 LREG x1, 1 * REGBYTES(sp) LREG x3, 3 * REGBYTES(sp) LREG x4, 4 * REGBYTES(sp) |