diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2018-12-12 06:12:40 -0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2018-12-18 09:56:27 +0800 |
| commit | 485e822346caa982a5c17b7b136b17e8d09dafee (patch) | |
| tree | 39c3ea6471f14e586c342ac78468958b3e25f0a9 /arch/riscv | |
| parent | 57fe5c64cb078c25c81cf40b5b268dc6857dc00c (diff) | |
riscv: Do some basic architecture level cpu initialization
In arch_cpu_init_dm() do some basic architecture level cpu
initialization, like FPU enable, etc.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/cpu.c | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index fc7c9b37516..e662140427a 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -8,6 +8,7 @@ #include <dm.h> #include <log.h> #include <asm/csr.h> +#include <asm/encoding.h> #include <dm/uclass-internal.h> /* @@ -61,7 +62,31 @@ static int riscv_cpu_probe(void) int arch_cpu_init_dm(void) { - return riscv_cpu_probe(); + int ret; + + ret = riscv_cpu_probe(); + if (ret) + return ret; + + /* Enable FPU */ + if (supports_extension('d') || supports_extension('f')) { + csr_set(MODE_PREFIX(status), MSTATUS_FS); + csr_write(fcsr, 0); + } + + if (CONFIG_IS_ENABLED(RISCV_MMODE)) { + /* + * Enable perf counters for cycle, time, + * and instret counters only + */ + csr_write(mcounteren, GENMASK(2, 0)); + + /* Disable paging */ + if (supports_extension('s')) + csr_write(satp, 0); + } + + return 0; } int arch_early_init_r(void) |