diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2018-12-12 06:12:42 -0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2018-12-18 09:56:27 +0800 |
| commit | 496262cca63f25408c6715b39cea1747e8ce9b59 (patch) | |
| tree | c8484b9d177173fa3220163ccace7c0ecb8203c3 /arch/riscv | |
| parent | 4b3f5ed5ac1a4376c29c3010d25049c03de4ed57 (diff) | |
riscv: Fix context restore before returning from trap handler
sp cannot be loaded before restoring other registers.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/mtrap.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S index a5ad558621..da307e4273 100644 --- a/arch/riscv/cpu/mtrap.S +++ b/arch/riscv/cpu/mtrap.S @@ -77,7 +77,6 @@ trap_entry: #endif csrs MODE_PREFIX(status), t0 LREG x1, 1 * REGBYTES(sp) - LREG x2, 2 * REGBYTES(sp) LREG x3, 3 * REGBYTES(sp) LREG x4, 4 * REGBYTES(sp) LREG x5, 5 * REGBYTES(sp) @@ -107,5 +106,6 @@ trap_entry: LREG x29, 29 * REGBYTES(sp) LREG x30, 30 * REGBYTES(sp) LREG x31, 31 * REGBYTES(sp) + LREG x2, 2 * REGBYTES(sp) addi sp, sp, 32 * REGBYTES MODE_PREFIX(ret) |