diff options
| author | Lukas Auer <lukas.auer@aisec.fraunhofer.de> | 2018-11-22 11:26:12 +0100 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2018-11-26 13:57:29 +0800 |
| commit | 862e2e75e8f317ff8bd660550d7da3fede2ead09 (patch) | |
| tree | 1c7affaf8b45a246101e92d149e5abc1c85267c1 /arch/riscv/lib | |
| parent | 17f2ffea36bf9d2ef7238cfd52b8872cbb50034a (diff) | |
riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I
RISC-V defines the base integer instruction sets as RV32I and RV64I.
Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to
match this convention.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/lib')
| -rw-r--r-- | arch/riscv/lib/setjmp.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/lib/setjmp.S b/arch/riscv/lib/setjmp.S index 8f5a6a23aad..72bc9241f6a 100644 --- a/arch/riscv/lib/setjmp.S +++ b/arch/riscv/lib/setjmp.S @@ -6,7 +6,7 @@ #include <config.h> #include <linux/linkage.h> -#ifdef CONFIG_CPU_RISCV_64 +#ifdef CONFIG_ARCH_RV64I #define STORE_IDX(reg, idx) sd reg, (idx*8)(a0) #define LOAD_IDX(reg, idx) ld reg, (idx*8)(a0) #else |