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authorLukas Auer <lukas.auer@aisec.fraunhofer.de>2019-12-08 23:28:50 +0100
committerAndes <uboot@andestech.com>2019-12-10 08:23:10 +0800
commit8b3e97badf97d6e399014fb4a152031f8a0c94ba (patch)
tree63c6e428e63506f5c1010b905159c67b178332f0 /arch/riscv/lib/andes_plic.c
parentb86f6d1e649f237849297b5ec6b5566b7a92b2b4 (diff)
riscv: add functions for reading the IPI status
Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/lib/andes_plic.c')
-rw-r--r--arch/riscv/lib/andes_plic.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 42394b9b6e..3868569a65 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -117,6 +117,17 @@ int riscv_clear_ipi(int hart)
return 0;
}
+int riscv_get_ipi(int hart, int *pending)
+{
+ PLIC_BASE_GET();
+
+ *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
+ gd->arch.boot_hart));
+ *pending = !!(*pending & SEND_IPI_TO_HART(hart));
+
+ return 0;
+}
+
static const struct udevice_id andes_plic_ids[] = {
{ .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
{ }