diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2018-12-12 06:12:37 -0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2018-12-18 09:56:27 +0800 |
| commit | 3967156464282df161f5e4be40999dae47adf799 (patch) | |
| tree | 4a1a5d03f2c44920b250cf9f3b1ad826f3634d8d /arch/riscv/include | |
| parent | ea53f1c74272bd7b1d9c8a28df4ac145c72131dd (diff) | |
riscv: Add exception codes for xcause register
This adds all exception codes in encoding.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/include')
| -rw-r--r-- | arch/riscv/include/asm/encoding.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 05e1ce3526..772668c74e 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -85,6 +85,21 @@ #define IRQ_COP 12 #define IRQ_HOST 13 +#define CAUSE_MISALIGNED_FETCH 0 +#define CAUSE_FETCH_ACCESS 1 +#define CAUSE_ILLEGAL_INSTRUCTION 2 +#define CAUSE_BREAKPOINT 3 +#define CAUSE_MISALIGNED_LOAD 4 +#define CAUSE_LOAD_ACCESS 5 +#define CAUSE_MISALIGNED_STORE 6 +#define CAUSE_STORE_ACCESS 7 +#define CAUSE_USER_ECALL 8 +#define CAUSE_SUPERVISOR_ECALL 9 +#define CAUSE_MACHINE_ECALL 11 +#define CAUSE_FETCH_PAGE_FAULT 12 +#define CAUSE_LOAD_PAGE_FAULT 13 +#define CAUSE_STORE_PAGE_FAULT 15 + #define DEFAULT_RSTVEC 0x00001000 #define DEFAULT_NMIVEC 0x00001004 #define DEFAULT_MTVEC 0x00001010 |