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authorRick Chen <rick@andestech.com>2019-08-28 18:46:10 +0800
committerAndes <uboot@andestech.com>2019-09-03 09:31:03 +0800
commitcf6ee112d802bc378172cfa5db3a430509cc82d8 (patch)
treee77e3abd86cff357bc1fcef571a142b436a40886 /arch/riscv/dts
parent7045ed9f1ad9bb2b8d19f3b5d39d7e1be8da36a6 (diff)
riscv: dts: move out AE350 L2 node from cpus node
When L2 node exists inside cpus node, uclass_get_device can not parse L2 node successfully. So move it outside from cpus node. Also add tag-ram-ctl and data-ram-ctl attributes for v5l2 cache controller driver. This can adjust timing by requirement from dtb to improve performance. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/riscv/dts')
-rw-r--r--arch/riscv/dts/ae350_32.dts17
-rw-r--r--arch/riscv/dts/ae350_64.dts17
2 files changed, 22 insertions, 12 deletions
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index cb6ee13f16..97b7cee983 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
+ };
- L2: l2-cache@e0500000 {
- compatible = "cache";
- cache-level = <2>;
- cache-size = <0x40000>;
- reg = <0x0 0xe0500000 0x0 0x40000>;
- };
+ L2: l2-cache@e0500000 {
+ compatible = "v5l2cache";
+ cache-level = <2>;
+ cache-size = <0x40000>;
+ reg = <0xe0500000 0x40000>;
+ andes,inst-prefetch = <3>;
+ andes,data-prefetch = <3>;
+ /* The value format is <XRAMOCTL XRAMICTL> */
+ andes,tag-ram-ctl = <0 0>;
+ andes,data-ram-ctl = <0 0>;
};
memory@0 {
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 705491a8e4..d8f00f8d3a 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
+ };
- L2: l2-cache@e0500000 {
- compatible = "cache";
- cache-level = <2>;
- cache-size = <0x40000>;
- reg = <0x0 0xe0500000 0x0 0x40000>;
- };
+ L2: l2-cache@e0500000 {
+ compatible = "v5l2cache";
+ cache-level = <2>;
+ cache-size = <0x40000>;
+ reg = <0x0 0xe0500000 0x0 0x40000>;
+ andes,inst-prefetch = <3>;
+ andes,data-prefetch = <3>;
+ /* The value format is <XRAMOCTL XRAMICTL> */
+ andes,tag-ram-ctl = <0 0>;
+ andes,data-ram-ctl = <0 0>;
};
memory@0 {