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authorSean Anderson <seanga2@gmail.com>2020-09-28 10:52:29 -0400
committerAndes <uboot@andestech.com>2020-09-30 08:54:46 +0800
commit422c3c5edf41318a3cdb532111148f085bc33638 (patch)
treea72db04431438960c3c675b4ba6ddc95e8b73e10 /arch/riscv/dts
parente89e8983dc6ae36e05694b0991dba78257241606 (diff)
riscv: Update SiFive device tree for new CLINT driver
We currently do this in a u-boot specific dts, but hopefully we can get these bindings added in Linux in the future. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
Diffstat (limited to 'arch/riscv/dts')
-rw-r--r--arch/riscv/dts/fu540-c000-u-boot.dtsi8
-rw-r--r--arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi4
2 files changed, 10 insertions, 2 deletions
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index 5302677ee4..a06e1b11c6 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -55,9 +55,13 @@
reg = <0x0 0x10070000 0x0 0x1000>;
fuse-count = <0x1000>;
};
- clint@2000000 {
+ clint: clint@2000000 {
compatible = "riscv,clint0";
- interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7 &cpu4_intc 3 &cpu4_intc 7>;
+ interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
+ &cpu1_intc 3 &cpu1_intc 7
+ &cpu2_intc 3 &cpu2_intc 7
+ &cpu3_intc 3 &cpu3_intc 7
+ &cpu4_intc 3 &cpu4_intc 7>;
reg = <0x0 0x2000000 0x0 0xc0000>;
u-boot,dm-spl;
};
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index 5d0c928b29..1996149c95 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -34,6 +34,10 @@
};
+&clint {
+ clocks = <&rtcclk>;
+};
+
&qspi0 {
u-boot,dm-spl;