diff options
| author | Pragnesh Patel <pragnesh.patel@sifive.com> | 2020-05-29 12:14:51 +0530 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-07-03 15:09:06 +0800 |
| commit | 5ce50206ed24080707946849d3542534fadf8cbf (patch) | |
| tree | 291e2af14db172b24773bc1a8c7c2b699b263d29 /arch/riscv/cpu/fu540/Makefile | |
| parent | edf4fc2bafac18399d07152be51cb77d5d1bb3ac (diff) | |
riscv: sifive: fu540: enable all cache ways from U-Boot proper
Add L2 cache node to enable all cache ways from U-Boot proper.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/riscv/cpu/fu540/Makefile')
| -rw-r--r-- | arch/riscv/cpu/fu540/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile index 043fb961a5..088205ef57 100644 --- a/arch/riscv/cpu/fu540/Makefile +++ b/arch/riscv/cpu/fu540/Makefile @@ -8,4 +8,5 @@ obj-y += spl.o else obj-y += dram.o obj-y += cpu.o +obj-y += cache.o endif |