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authorBin Meng <bmeng.cn@gmail.com>2018-09-26 06:55:17 -0700
committerAndes <uboot@andestech.com>2018-10-03 17:48:14 +0800
commitb5369c5813aa407139fc137ccbd0944190f15ebc (patch)
treea344c53febb288b4e740dce7cc70c3efa91580fc /arch/riscv/Makefile
parented49ba4dcccb21cee1c32427cf5bbf09521cd8dd (diff)
riscv: Make start.S available for all targets
Currently start.S is inside arch/riscv/cpu/ax25/, but it can be common for all RISC-V targets. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Diffstat (limited to 'arch/riscv/Makefile')
-rw-r--r--arch/riscv/Makefile2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index af432e16ff..8fb6a889d8 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -3,7 +3,7 @@
# Copyright (C) 2017 Andes Technology Corporation.
# Rick Chen, Andes Technology Corporation <rick@andestech.com>
-head-y := arch/riscv/cpu/$(CPU)/start.o
+head-y := arch/riscv/cpu/start.o
libs-y += arch/riscv/cpu/
libs-y += arch/riscv/cpu/$(CPU)/