diff options
| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2019-05-22 22:46:03 +0800 |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2019-06-20 10:43:55 +0530 |
| commit | c16dfd016afb92771d425ae84a2949da1d7e112b (patch) | |
| tree | f0d1535253ccb9b0e00ef40dbaa929f372b16961 /arch/powerpc | |
| parent | 77f6e2dd0551d8a825bab391a1bd6b838874bcd4 (diff) | |
powerpc: mpc85xx: Move CONFIG_FSL_PCIE_DISABLE_ASPM to Kconfig
Use the Kconfig option to select the PCIe ASPM errata.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/Kconfig | 8 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 5 |
2 files changed, 8 insertions, 5 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index aebf168a89..6c3c164883 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -702,6 +702,7 @@ config ARCH_P1011 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_DISABLE_ASPM select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -716,6 +717,7 @@ config ARCH_P1020 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_DISABLE_ASPM select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -735,6 +737,7 @@ config ARCH_P1021 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_DISABLE_ASPM select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -782,6 +785,7 @@ config ARCH_P1024 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_DISABLE_ASPM select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -802,6 +806,7 @@ config ARCH_P1025 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_DISABLE_ASPM select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -1429,6 +1434,9 @@ config SYS_P4080_ERRATUM_SERDES_A001 config SYS_P4080_ERRATUM_SERDES_A005 bool +config FSL_PCIE_DISABLE_ASPM + bool + config SYS_FSL_QORIQ_CHASSIS1 bool diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 7c963cdc35..946e74a93b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -61,19 +61,16 @@ /* P1011 is single core version of P1020 */ #elif defined(CONFIG_ARCH_P1011) #define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #elif defined(CONFIG_ARCH_P1020) #define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif #elif defined(CONFIG_ARCH_P1021) #define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 @@ -95,14 +92,12 @@ /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_ARCH_P1024) #define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* P1025 is lower end variant of P1021 */ #elif defined(CONFIG_ARCH_P1025) #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 |