diff options
author | Tom Rini <trini@konsulko.com> | 2022-10-28 20:27:13 -0400 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2022-11-10 10:08:55 -0500 |
commit | 6cc04547cb3bbd3a3d78947f200acbae19e3c67f (patch) | |
tree | 518a634e223bfb02d08ca359331a4ec08c20513c /arch/powerpc/include | |
parent | 5155207ae1a0797a99c0a5f4e99741960ff04697 (diff) |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 81 | ||||
-rw-r--r-- | arch/powerpc/include/asm/fsl_liodn.h | 56 | ||||
-rw-r--r-- | arch/powerpc/include/asm/immap_83xx.h | 2 | ||||
-rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 212 |
4 files changed, 175 insertions, 176 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index d3d4e9c053f..25d1b486174 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -17,10 +17,10 @@ #include <fsl_ddrc_version.h> #if defined(CONFIG_ARCH_MPC8548) -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CFG_SYS_FSL_SRIO_MAX_PORTS 1 +#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 @@ -59,30 +59,30 @@ #define QE_NUM_OF_SNUM 28 #elif defined(CONFIG_ARCH_P2020) -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 +#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #elif defined(CONFIG_ARCH_P3041) #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 +#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ #define CONFIG_SYS_NUM_FMAN 2 @@ -91,11 +91,11 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 -#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 +#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 #elif defined(CONFIG_ARCH_P5040) #define CONFIG_SYS_NUM_FMAN 2 @@ -104,7 +104,7 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 5 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 +#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #elif defined(CONFIG_ARCH_BSC9131) #define CONFIG_FSL_SDHC_V2_3 @@ -118,7 +118,7 @@ #elif defined(CONFIG_ARCH_T4240) #ifdef CONFIG_ARCH_T4240 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } +#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 2 #define CONFIG_SYS_NUM_FM2_DTSEC 8 @@ -131,17 +131,17 @@ #endif #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 -#define CONFIG_SYS_FSL_SRDS_3 -#define CONFIG_SYS_FSL_SRDS_4 +#define CFG_SYS_FSL_SRDS_3 +#define CFG_SYS_FSL_SRDS_4 #define CONFIG_SYS_NUM_FMAN 2 #define CONFIG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM1_CLK 3 #define CONFIG_SYS_FM2_CLK 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) #define CONFIG_SYS_FSL_SRDS_1 @@ -154,21 +154,21 @@ #ifdef CONFIG_ARCH_B4860 #define CONFIG_MAX_DSP_CPUS 12 #define CONFIG_NUM_DSP_CPUS 6 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } +#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #else #define CONFIG_MAX_DSP_CPUS 2 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } +#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 0 #endif #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } +#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 @@ -184,8 +184,7 @@ #define QE_NUM_OF_SNUM 28 #elif defined(CONFIG_ARCH_T1024) -#define CONFIG_SYS_FSL_NUM_CC_PLL 2 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } +#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 4 @@ -202,15 +201,15 @@ #elif defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } +#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_FSL_SRDS_1 #if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 4 #define CONFIG_SYS_FSL_SRDS_2 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #endif #define CONFIG_PME_PLAT_CLK_DIV 1 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV @@ -224,7 +223,7 @@ #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2_1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 +#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000 #endif diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index be55f99030e..de85bcfdcf9 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -33,7 +33,7 @@ struct srio_liodn_id_table { { .id = { id_a }, .num_ids = 1, .portid = port, \ .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \ + (port - 1) * 0x200 \ - + CONFIG_SYS_FSL_SRIO_ADDR, \ + + CFG_SYS_FSL_SRIO_ADDR, \ } struct liodn_id_table { @@ -130,29 +130,29 @@ extern void fdt_fixup_liodn(void *blob); #define SET_QMAN_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,qman", liodn, \ offsetof(struct ccsr_qman, liodnr) + \ - CONFIG_SYS_FSL_QMAN_OFFSET, \ - CONFIG_SYS_FSL_QMAN_OFFSET) + CFG_SYS_FSL_QMAN_OFFSET, \ + CFG_SYS_FSL_QMAN_OFFSET) #define SET_BMAN_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,bman", liodn, \ offsetof(struct ccsr_bman, liodnr) + \ - CONFIG_SYS_FSL_BMAN_OFFSET, \ - CONFIG_SYS_FSL_BMAN_OFFSET) + CFG_SYS_FSL_BMAN_OFFSET, \ + CFG_SYS_FSL_BMAN_OFFSET) #define SET_PME_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \ - CONFIG_SYS_FSL_CORENET_PME_OFFSET, \ - CONFIG_SYS_FSL_CORENET_PME_OFFSET) + CFG_SYS_FSL_CORENET_PME_OFFSET, \ + CFG_SYS_FSL_CORENET_PME_OFFSET) #define SET_PMAN_LIODN(num, liodn) \ SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \ offsetof(struct ccsr_pman, ppa1) + \ - CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \ - CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET) + CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \ + CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET) /* -1 from portID due to how immap has the registers */ #define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \ - CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \ + CFG_SYS_FSL_FM##fmNum##_OFFSET + \ offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1]) #ifdef CONFIG_SYS_FMAN_V3 @@ -160,31 +160,31 @@ extern void fdt_fixup_liodn(void *blob); #define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \ SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx", \ liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ - CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) + CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) /* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */ #define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \ SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \ liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ - CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) + CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) /* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */ #define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \ SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \ liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ - CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) + CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) #else /* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */ #define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \ SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-1g-rx", \ liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ - CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) + CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) /* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */ #define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \ SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-10g-rx", \ liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ - CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) + CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) #endif /* * handle both old and new versioned SEC properties: @@ -193,44 +193,44 @@ extern void fdt_fixup_liodn(void *blob); #define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \ SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\ offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \ + CFG_SYS_FSL_SEC_OFFSET, \ + CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \ SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\ offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum) + CFG_SYS_FSL_SEC_OFFSET, \ + CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum) /* This is a bit evil since we treat rtic param as both a string & hex value */ #define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \ SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \ liodnA, \ offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \ + CFG_SYS_FSL_SEC_OFFSET, \ + CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \ SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \ liodnA, \ offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)) + CFG_SYS_FSL_SEC_OFFSET, \ + CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)) #define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \ SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \ offsetof(ccsr_sec_t, decoliodnr[num].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, 0) + CFG_SYS_FSL_SEC_OFFSET, 0) #define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \ SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \ liodnA, \ offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg1) + \ - CONFIG_SYS_FSL_RAID_ENGINE_OFFSET, \ + CFG_SYS_FSL_RAID_ENGINE_OFFSET, \ offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \ - CONFIG_SYS_FSL_RAID_ENGINE_OFFSET) + CFG_SYS_FSL_RAID_ENGINE_OFFSET) #define SET_RMAN_LIODN(ibNum, liodn) \ SET_LIODN_ENTRY_1("fsl,rman-inbound-block", liodn, \ offsetof(struct ccsr_rman, mmitdr) + \ - CONFIG_SYS_FSL_CORENET_RMAN_OFFSET, \ - CONFIG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000) + CFG_SYS_FSL_CORENET_RMAN_OFFSET, \ + CFG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000) extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[]; extern struct liodn_id_table raide_liodn_tbl[]; diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 0bf5b9c2ba5..8e182026708 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -862,7 +862,7 @@ struct ccsr_gpio { }; #define CFG_SYS_MPC8xxx_DDR_OFFSET (0x2000) -#define CONFIG_SYS_FSL_DDR_ADDR \ +#define CFG_SYS_FSL_DDR_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET) #define CFG_SYS_MPC83xx_DMA_OFFSET (0x8000) #define CFG_SYS_MPC83xx_DMA_ADDR \ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 7a7a7f2113c..c9ced5474c2 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -963,7 +963,7 @@ struct rio_lp_serial { u32 prtoccsr; /* Port Response Time-out CCSR */ u8 res1[20]; u32 pgccsr; /* Port General CSR */ - struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; + struct rio_lp_serial_port port[CFG_SYS_FSL_SRIO_MAX_PORTS]; }; /* Logical error reporting registers */ @@ -993,7 +993,7 @@ struct rio_phys_err_port { /* Physical error reporting registers */ struct rio_phys_err { - struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; + struct rio_phys_err_port port[CFG_SYS_FSL_SRIO_MAX_PORTS]; }; /* Implementation Space: General Port-Common */ @@ -1033,7 +1033,7 @@ struct rio_impl_port_spec { /* Implementation Space: register */ struct rio_implement { struct rio_impl_common com; - struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; + struct rio_impl_port_spec port[CFG_SYS_FSL_SRIO_MAX_PORTS]; }; /* Revision Control Register */ @@ -1061,13 +1061,13 @@ struct rio_atmu_riw { /* ATMU window registers */ struct rio_atmu_win { - struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM]; + struct rio_atmu_row outbw[CFG_SYS_FSL_SRIO_OB_WIN_NUM]; u8 res0[64]; - struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM]; + struct rio_atmu_riw inbw[CFG_SYS_FSL_SRIO_IB_WIN_NUM]; }; struct rio_atmu { - struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; + struct rio_atmu_win port[CFG_SYS_FSL_SRIO_MAX_PORTS]; }; #ifdef CONFIG_SYS_FSL_RMU @@ -1154,7 +1154,7 @@ struct ccsr_rio { struct rio_atmu atmu; #ifdef CONFIG_SYS_FSL_RMU u8 res5[8192]; - struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM]; + struct rio_msg msg[CFG_SYS_FSL_SRIO_MSG_UNIT_NUM]; u8 res6[512]; struct rio_dbell dbell; u8 res7[100]; @@ -1162,7 +1162,7 @@ struct ccsr_rio { #endif #ifdef CONFIG_SYS_FSL_SRIO_LIODN u8 res5[8192]; - struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; + struct rio_liodn liodn[CFG_SYS_FSL_SRIO_MAX_PORTS]; #endif }; #endif @@ -2431,17 +2431,17 @@ struct ccsr_pman { #endif #ifdef CONFIG_FSL_CORENET -#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 +#define CFG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 #ifdef CONFIG_SYS_PMAN -#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000 -#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000 -#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000 +#define CFG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000 +#define CFG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000 +#define CFG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000 #endif #define CFG_SYS_MPC8xxx_DDR_OFFSET 0x8000 #define CFG_SYS_MPC8xxx_DDR2_OFFSET 0x9000 #define CFG_SYS_MPC8xxx_DDR3_OFFSET 0xA000 -#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 -#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 +#define CFG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 +#define CFG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 #ifdef CONFIG_SYS_FSL_SFP_VER_3_0 /* In SFPv3, OSPR register is now at offset 0x200. * * So directly mapping sfp register map to this address */ @@ -2450,13 +2450,13 @@ struct ccsr_pman { #else #define CONFIG_SYS_SFP_OFFSET 0xE8000 #endif -#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 -#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 -#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000 -#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000 -#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 -#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000 -#define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000 +#define CFG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 +#define CFG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 +#define CFG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000 +#define CFG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000 +#define CFG_SYS_FSL_CPC_OFFSET 0x10000 +#define CFG_SYS_FSL_SCFG_OFFSET 0xFC000 +#define CFG_SYS_FSL_PAMU_OFFSET 0x20000 #define CFG_SYS_MPC85xx_DMA1_OFFSET 0x100000 #define CFG_SYS_MPC85xx_DMA2_OFFSET 0x101000 #define CFG_SYS_MPC85xx_DMA3_OFFSET 0x102000 @@ -2468,7 +2468,7 @@ struct ccsr_pman { #define CFG_SYS_MPC85xx_GPIO_OFFSET 0x130000 #define CFG_SYS_MPC85xx_TDM_OFFSET 0x185000 #define CFG_SYS_MPC85xx_QE_OFFSET 0x140000 -#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 +#define CFG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \ !defined(CONFIG_ARCH_B4420) #define CFG_SYS_MPC85xx_PCIE1_OFFSET 0x240000 @@ -2487,33 +2487,33 @@ struct ccsr_pman { #define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100 #define CFG_SYS_MPC85xx_SATA1_OFFSET 0x220000 #define CFG_SYS_MPC85xx_SATA2_OFFSET 0x221000 -#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 -#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000 +#define CFG_SYS_FSL_SEC_OFFSET 0x300000 +#define CFG_SYS_FSL_JR0_OFFSET 0x301000 #define CONFIG_SYS_SEC_MON_OFFSET 0x314000 -#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 -#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000 -#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000 -#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000 -#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000 -#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000 -#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000 -#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000 -#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000 -#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000 -#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000 -#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000 -#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000 -#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000 -#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000 -#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000 -#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000 -#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000 -#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000 -#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000 -#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000 -#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000 -#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000 -#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000 +#define CFG_SYS_FSL_CORENET_PME_OFFSET 0x316000 +#define CFG_SYS_FSL_QMAN_OFFSET 0x318000 +#define CFG_SYS_FSL_BMAN_OFFSET 0x31a000 +#define CFG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000 +#define CFG_SYS_FSL_FM1_OFFSET 0x400000 +#define CFG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000 +#define CFG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000 +#define CFG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000 +#define CFG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000 +#define CFG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000 +#define CFG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000 +#define CFG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000 +#define CFG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000 +#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000 +#define CFG_SYS_FSL_FM2_OFFSET 0x500000 +#define CFG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000 +#define CFG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000 +#define CFG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000 +#define CFG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000 +#define CFG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000 +#define CFG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000 +#define CFG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000 +#define CFG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000 +#define CFG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000 #else #define CFG_SYS_MPC85xx_ECM_OFFSET 0x0000 #define CFG_SYS_MPC8xxx_DDR_OFFSET 0x2000 @@ -2551,57 +2551,57 @@ struct ccsr_pman { #define CONFIG_SYS_MDIO1_OFFSET 0x24000 #define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 #if defined(CONFIG_ARCH_C29X) -#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000 -#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000 +#define CFG_SYS_FSL_SEC_OFFSET 0x80000 +#define CFG_SYS_FSL_JR0_OFFSET 0x81000 #else -#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000 -#define CONFIG_SYS_FSL_JR0_OFFSET 0x31000 +#define CFG_SYS_FSL_SEC_OFFSET 0x30000 +#define CFG_SYS_FSL_JR0_OFFSET 0x31000 #endif #define CFG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CFG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 #define CONFIG_SYS_SEC_MON_OFFSET 0xE6000 #define CONFIG_SYS_SFP_OFFSET 0xE7000 -#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000 -#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000 -#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000 -#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000 -#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000 -#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000 +#define CFG_SYS_FSL_QMAN_OFFSET 0x88000 +#define CFG_SYS_FSL_BMAN_OFFSET 0x8a000 +#define CFG_SYS_FSL_FM1_OFFSET 0x100000 +#define CFG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000 +#define CFG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000 +#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000 #endif #define CFG_SYS_MPC85xx_PIC_OFFSET 0x40000 #define CFG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 -#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000 - -#define CONFIG_SYS_FSL_CPC_ADDR \ - (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) -#define CONFIG_SYS_FSL_SCFG_ADDR \ - (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET) -#define CONFIG_SYS_FSL_QMAN_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) -#define CONFIG_SYS_FSL_BMAN_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET) -#define CONFIG_SYS_FSL_CORENET_PME_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET) -#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET) -#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET) +#define CFG_SYS_FSL_SRIO_OFFSET 0xC0000 + +#define CFG_SYS_FSL_CPC_ADDR \ + (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET) +#define CFG_SYS_FSL_SCFG_ADDR \ + (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET) +#define CFG_SYS_FSL_QMAN_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_QMAN_OFFSET) +#define CFG_SYS_FSL_BMAN_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_BMAN_OFFSET) +#define CFG_SYS_FSL_CORENET_PME_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_PME_OFFSET) +#define CFG_SYS_FSL_RAID_ENGINE_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_RAID_ENGINE_OFFSET) +#define CFG_SYS_FSL_CORENET_RMAN_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RMAN_OFFSET) #define CFG_SYS_MPC85xx_GUTS_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GUTS_OFFSET) -#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) -#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) -#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) +#define CFG_SYS_FSL_CORENET_CCM_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CCM_OFFSET) +#define CFG_SYS_FSL_CORENET_CLK_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CLK_OFFSET) +#define CFG_SYS_FSL_CORENET_RCPM_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RCPM_OFFSET) #define CFG_SYS_MPC85xx_ECM_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ECM_OFFSET) -#define CONFIG_SYS_FSL_DDR_ADDR \ +#define CFG_SYS_FSL_DDR_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET) -#define CONFIG_SYS_FSL_DDR2_ADDR \ +#define CFG_SYS_FSL_DDR2_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET) -#define CONFIG_SYS_FSL_DDR3_ADDR \ +#define CFG_SYS_FSL_DDR3_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET) #define CONFIG_SYS_LBC_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET) @@ -2631,14 +2631,14 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES1_OFFSET) #define CFG_SYS_MPC85xx_SERDES2_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES2_OFFSET) -#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) -#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET) -#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET) -#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET) +#define CFG_SYS_FSL_CORENET_SERDES_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES_OFFSET) +#define CFG_SYS_FSL_CORENET_SERDES2_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES2_OFFSET) +#define CFG_SYS_FSL_CORENET_SERDES3_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES3_OFFSET) +#define CFG_SYS_FSL_CORENET_SERDES4_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES4_OFFSET) #define CFG_SYS_MPC85xx_USB1_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_OFFSET) #define CFG_SYS_MPC85xx_USB2_ADDR \ @@ -2647,20 +2647,20 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_PHY_OFFSET) #define CFG_SYS_MPC85xx_USB2_PHY_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_PHY_OFFSET) -#define CONFIG_SYS_FSL_SEC_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) -#define CONFIG_SYS_FSL_JR0_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) -#define CONFIG_SYS_FSL_FM1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) -#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) -#define CONFIG_SYS_FSL_FM2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET) -#define CONFIG_SYS_FSL_SRIO_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET) +#define CFG_SYS_FSL_SEC_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET) +#define CFG_SYS_FSL_JR0_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET) +#define CFG_SYS_FSL_FM1_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_OFFSET) +#define CFG_SYS_FSL_FM1_DTSEC1_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_DTSEC1_OFFSET) +#define CFG_SYS_FSL_FM2_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM2_OFFSET) +#define CFG_SYS_FSL_SRIO_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_SRIO_OFFSET) #define CONFIG_SYS_PAMU_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET) #define CONFIG_SYS_PCI1_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI1_OFFSET) @@ -2739,8 +2739,8 @@ struct ccsr_cluster_l2 { u32 l2erraddr; /* 0xe54 L2 cache error address */ u32 l2errctl; /* 0xe58 L2 cache error control */ }; -#define CONFIG_SYS_FSL_CLUSTER_1_L2 \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET) +#define CFG_SYS_FSL_CLUSTER_1_L2 \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CLUSTER_1_L2_OFFSET) #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000 |