global: Migrate CONFIG_SYS_MPC8* symbols to the CFG_SYS namespace

Migrate all of COFIG_SYS_MPC* to the CFG_SYS namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>

4 files changed, 129 insertions, 129 deletions

diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index 7ced50c1d4..be55f99030 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -18,15 +18,15 @@ struct srio_liodn_id_table {
 #define SET_SRIO_LIODN_1(port, idA) \
 	{ .id = { idA }, .num_ids = 1, .portid = port, \
 	  .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
-		+ CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
 	}
 
 #define SET_SRIO_LIODN_2(port, idA, idB) \
 	{ .id = { idA, idB }, .num_ids = 2, .portid = port, \
 	  .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
-		+ CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
 	  .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
-		+ CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+		+ CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
 	}
 
 #define SET_SRIO_LIODN_BASE(port, id_a) \
@@ -90,42 +90,42 @@ extern void fdt_fixup_liodn(void *blob);
 
 #define SET_GUTS_LIODN(compat, liodn, name, compatoff) \
 	SET_LIODN_ENTRY_1(compat, liodn, \
-		offsetof(ccsr_gur_t, name) + CONFIG_SYS_MPC85xx_GUTS_OFFSET, \
+		offsetof(ccsr_gur_t, name) + CFG_SYS_MPC85xx_GUTS_OFFSET, \
 		compatoff)
 
 #define SET_USB_LIODN(usbNum, compat, liodn) \
 	SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\
-		CONFIG_SYS_MPC85xx_USB##usbNum##_OFFSET)
+		CFG_SYS_MPC85xx_USB##usbNum##_OFFSET)
 
 #define SET_SATA_LIODN(sataNum, liodn) \
 	SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\
-		CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
+		CFG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
 
 #define SET_PCI_LIODN(compat, pciNum, liodn) \
 	SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
-		CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+		CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
 
 #define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
 	SET_LIODN_ENTRY_1(compat, liodn,\
-		offsetof(ccsr_pcix_t, liodn_base) + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
-		CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+		offsetof(ccsr_pcix_t, liodn_base) + CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
+		CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
 
 /* reg nodes for DMA start @ 0x300 */
 #define SET_DMA_LIODN(dmaNum, compat, liodn) \
 	SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\
-		CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
+		CFG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
 
 #define SET_SDHC_LIODN(sdhcNum, liodn) \
 	SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
-		CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
+		CFG_SYS_MPC85xx_ESDHC_OFFSET)
 
 #define SET_QE_LIODN(liodn) \
 	SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
-		CONFIG_SYS_MPC85xx_QE_OFFSET)
+		CFG_SYS_MPC85xx_QE_OFFSET)
 
 #define SET_TDM_LIODN(liodn) \
 	SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\
-		CONFIG_SYS_MPC85xx_TDM_OFFSET)
+		CFG_SYS_MPC85xx_TDM_OFFSET)
 
 #define SET_QMAN_LIODN(liodn) \
 	SET_LIODN_ENTRY_1("fsl,qman", liodn, \
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index c7313472de..0bf5b9c2ba 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -861,15 +861,15 @@ struct ccsr_gpio {
 	};
 };
 
-#define CONFIG_SYS_MPC8xxx_DDR_OFFSET	(0x2000)
+#define CFG_SYS_MPC8xxx_DDR_OFFSET	(0x2000)
 #define CONFIG_SYS_FSL_DDR_ADDR \
-			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
-#define CONFIG_SYS_MPC83xx_DMA_OFFSET	(0x8000)
-#define CONFIG_SYS_MPC83xx_DMA_ADDR \
-			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
-#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET	(0x2e000)
-#define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
-			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
+			(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
+#define CFG_SYS_MPC83xx_DMA_OFFSET	(0x8000)
+#define CFG_SYS_MPC83xx_DMA_ADDR \
+			(CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_DMA_OFFSET)
+#define CFG_SYS_MPC83xx_ESDHC_OFFSET	(0x2e000)
+#define CFG_SYS_MPC83xx_ESDHC_ADDR \
+			(CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_ESDHC_OFFSET)
 
 #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
 
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 7e88779227..7a7a7f2113 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2437,9 +2437,9 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET	0x5000
 #define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET	0x6000
 #endif
-#define CONFIG_SYS_MPC8xxx_DDR_OFFSET		0x8000
-#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET		0x9000
-#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET		0xA000
+#define CFG_SYS_MPC8xxx_DDR_OFFSET		0x8000
+#define CFG_SYS_MPC8xxx_DDR2_OFFSET		0x9000
+#define CFG_SYS_MPC8xxx_DDR3_OFFSET		0xA000
 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET	0xE1000
 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET	0xE2000
 #ifdef CONFIG_SYS_FSL_SFP_VER_3_0
@@ -2457,36 +2457,36 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_CPC_OFFSET		0x10000
 #define CONFIG_SYS_FSL_SCFG_OFFSET		0xFC000
 #define CONFIG_SYS_FSL_PAMU_OFFSET		0x20000
-#define CONFIG_SYS_MPC85xx_DMA1_OFFSET		0x100000
-#define CONFIG_SYS_MPC85xx_DMA2_OFFSET		0x101000
-#define CONFIG_SYS_MPC85xx_DMA3_OFFSET		0x102000
-#define CONFIG_SYS_MPC85xx_DMA_OFFSET		CONFIG_SYS_MPC85xx_DMA1_OFFSET
-#define CONFIG_SYS_MPC85xx_ESPI_OFFSET		0x110000
-#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x114000
-#define CONFIG_SYS_MPC85xx_LBC_OFFSET		0x124000
-#define CONFIG_SYS_MPC85xx_IFC_OFFSET		0x124000
-#define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0x130000
-#define CONFIG_SYS_MPC85xx_TDM_OFFSET		0x185000
-#define CONFIG_SYS_MPC85xx_QE_OFFSET		0x140000
+#define CFG_SYS_MPC85xx_DMA1_OFFSET		0x100000
+#define CFG_SYS_MPC85xx_DMA2_OFFSET		0x101000
+#define CFG_SYS_MPC85xx_DMA3_OFFSET		0x102000
+#define CFG_SYS_MPC85xx_DMA_OFFSET		CFG_SYS_MPC85xx_DMA1_OFFSET
+#define CFG_SYS_MPC85xx_ESPI_OFFSET		0x110000
+#define CFG_SYS_MPC85xx_ESDHC_OFFSET		0x114000
+#define CFG_SYS_MPC85xx_LBC_OFFSET		0x124000
+#define CFG_SYS_MPC85xx_IFC_OFFSET		0x124000
+#define CFG_SYS_MPC85xx_GPIO_OFFSET		0x130000
+#define CFG_SYS_MPC85xx_TDM_OFFSET		0x185000
+#define CFG_SYS_MPC85xx_QE_OFFSET		0x140000
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET	0x1e0000
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
 	!defined(CONFIG_ARCH_B4420)
-#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET		0x240000
-#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET		0x250000
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET		0x260000
-#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET		0x270000
+#define CFG_SYS_MPC85xx_PCIE1_OFFSET		0x240000
+#define CFG_SYS_MPC85xx_PCIE2_OFFSET		0x250000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET		0x260000
+#define CFG_SYS_MPC85xx_PCIE4_OFFSET		0x270000
 #else
-#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET		0x200000
-#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET		0x201000
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET		0x202000
-#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET		0x203000
+#define CFG_SYS_MPC85xx_PCIE1_OFFSET		0x200000
+#define CFG_SYS_MPC85xx_PCIE2_OFFSET		0x201000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET		0x202000
+#define CFG_SYS_MPC85xx_PCIE4_OFFSET		0x203000
 #endif
-#define CONFIG_SYS_MPC85xx_USB1_OFFSET		0x210000
-#define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x211000
-#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
-#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
-#define CONFIG_SYS_MPC85xx_SATA1_OFFSET		0x220000
-#define CONFIG_SYS_MPC85xx_SATA2_OFFSET		0x221000
+#define CFG_SYS_MPC85xx_USB1_OFFSET		0x210000
+#define CFG_SYS_MPC85xx_USB2_OFFSET		0x211000
+#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
+#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
+#define CFG_SYS_MPC85xx_SATA1_OFFSET		0x220000
+#define CFG_SYS_MPC85xx_SATA2_OFFSET		0x221000
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x300000
 #define CONFIG_SYS_FSL_JR0_OFFSET		0x301000
 #define CONFIG_SYS_SEC_MON_OFFSET		0x314000
@@ -2515,32 +2515,32 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET	0x591000
 #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET	0xC20000
 #else
-#define CONFIG_SYS_MPC85xx_ECM_OFFSET		0x0000
-#define CONFIG_SYS_MPC8xxx_DDR_OFFSET		0x2000
-#define CONFIG_SYS_MPC85xx_LBC_OFFSET		0x5000
-#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET		0x6000
-#define CONFIG_SYS_MPC85xx_ESPI_OFFSET		0x7000
-#define CONFIG_SYS_MPC85xx_PCI1_OFFSET		0x8000
-#define CONFIG_SYS_MPC85xx_PCIX_OFFSET		0x8000
-#define CONFIG_SYS_MPC85xx_PCI2_OFFSET		0x9000
-#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET		0x9000
-#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET         0xa000
-#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET         0x9000
+#define CFG_SYS_MPC85xx_ECM_OFFSET		0x0000
+#define CFG_SYS_MPC8xxx_DDR_OFFSET		0x2000
+#define CFG_SYS_MPC85xx_LBC_OFFSET		0x5000
+#define CFG_SYS_MPC8xxx_DDR2_OFFSET		0x6000
+#define CFG_SYS_MPC85xx_ESPI_OFFSET		0x7000
+#define CFG_SYS_MPC85xx_PCI1_OFFSET		0x8000
+#define CFG_SYS_MPC85xx_PCIX_OFFSET		0x8000
+#define CFG_SYS_MPC85xx_PCI2_OFFSET		0x9000
+#define CFG_SYS_MPC85xx_PCIX2_OFFSET		0x9000
+#define CFG_SYS_MPC85xx_PCIE1_OFFSET         0xa000
+#define CFG_SYS_MPC85xx_PCIE2_OFFSET         0x9000
 #if defined(CONFIG_ARCH_P2020)
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET         0x8000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET         0x8000
 #else
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET         0xb000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET         0xb000
 #endif
-#define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0xF000
-#define CONFIG_SYS_MPC85xx_SATA1_OFFSET		0x18000
-#define CONFIG_SYS_MPC85xx_SATA2_OFFSET		0x19000
-#define CONFIG_SYS_MPC85xx_IFC_OFFSET		0x1e000
-#define CONFIG_SYS_MPC85xx_L2_OFFSET		0x20000
-#define CONFIG_SYS_MPC85xx_DMA_OFFSET		0x21000
-#define CONFIG_SYS_MPC85xx_USB1_OFFSET		0x22000
-#define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x23000
-#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET	0xE5000
-#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET	0xE5100
+#define CFG_SYS_MPC85xx_GPIO_OFFSET		0xF000
+#define CFG_SYS_MPC85xx_SATA1_OFFSET		0x18000
+#define CFG_SYS_MPC85xx_SATA2_OFFSET		0x19000
+#define CFG_SYS_MPC85xx_IFC_OFFSET		0x1e000
+#define CFG_SYS_MPC85xx_L2_OFFSET		0x20000
+#define CFG_SYS_MPC85xx_DMA_OFFSET		0x21000
+#define CFG_SYS_MPC85xx_USB1_OFFSET		0x22000
+#define CFG_SYS_MPC85xx_USB2_OFFSET		0x23000
+#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET	0xE5000
+#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET	0xE5100
 #ifdef CONFIG_TSECV2
 #define CONFIG_SYS_TSEC1_OFFSET			0xB0000
 #elif defined(CONFIG_TSECV2_1)
@@ -2549,7 +2549,7 @@ struct ccsr_pman {
 #define CONFIG_SYS_TSEC1_OFFSET			0x24000
 #endif
 #define CONFIG_SYS_MDIO1_OFFSET			0x24000
-#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
+#define CFG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
 #if defined(CONFIG_ARCH_C29X)
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x80000
 #define CONFIG_SYS_FSL_JR0_OFFSET               0x81000
@@ -2557,8 +2557,8 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x30000
 #define CONFIG_SYS_FSL_JR0_OFFSET               0x31000
 #endif
-#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
-#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
+#define CFG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
+#define CFG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
 #define CONFIG_SYS_SEC_MON_OFFSET		0xE6000
 #define CONFIG_SYS_SFP_OFFSET			0xE7000
 #define CONFIG_SYS_FSL_QMAN_OFFSET		0x88000
@@ -2569,8 +2569,8 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0x1e0000
 #endif
 
-#define CONFIG_SYS_MPC85xx_PIC_OFFSET		0x40000
-#define CONFIG_SYS_MPC85xx_GUTS_OFFSET		0xE0000
+#define CFG_SYS_MPC85xx_PIC_OFFSET		0x40000
+#define CFG_SYS_MPC85xx_GUTS_OFFSET		0xE0000
 #define CONFIG_SYS_FSL_SRIO_OFFSET		0xC0000
 
 #define CONFIG_SYS_FSL_CPC_ADDR	\
@@ -2587,50 +2587,50 @@ struct ccsr_pman {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
-#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
+#define CFG_SYS_MPC85xx_GUTS_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GUTS_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
-#define CONFIG_SYS_MPC85xx_ECM_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
+#define CFG_SYS_MPC85xx_ECM_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ECM_OFFSET)
 #define CONFIG_SYS_FSL_DDR_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
 #define CONFIG_SYS_FSL_DDR2_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET)
 #define CONFIG_SYS_FSL_DDR3_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET)
 #define CONFIG_SYS_LBC_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET)
 #define CONFIG_SYS_IFC_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
-#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
-#define CONFIG_SYS_MPC85xx_PCIX_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
-#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
-#define CONFIG_SYS_MPC85xx_GPIO_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
-#define CONFIG_SYS_MPC85xx_SATA1_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
-#define CONFIG_SYS_MPC85xx_SATA2_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
-#define CONFIG_SYS_MPC85xx_L2_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
-#define CONFIG_SYS_MPC85xx_DMA_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
-#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
-#define CONFIG_SYS_MPC8xxx_PIC_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
-#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
-#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_IFC_OFFSET)
+#define CFG_SYS_MPC85xx_ESPI_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESPI_OFFSET)
+#define CFG_SYS_MPC85xx_PCIX_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIX_OFFSET)
+#define CFG_SYS_MPC85xx_PCIX2_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIX2_OFFSET)
+#define CFG_SYS_MPC85xx_GPIO_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GPIO_OFFSET)
+#define CFG_SYS_MPC85xx_SATA1_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SATA1_OFFSET)
+#define CFG_SYS_MPC85xx_SATA2_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SATA2_OFFSET)
+#define CFG_SYS_MPC85xx_L2_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_L2_OFFSET)
+#define CFG_SYS_MPC85xx_DMA_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_DMA_OFFSET)
+#define CFG_SYS_MPC85xx_ESDHC_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESDHC_OFFSET)
+#define CFG_SYS_MPC8xxx_PIC_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PIC_OFFSET)
+#define CFG_SYS_MPC85xx_SERDES1_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES1_OFFSET)
+#define CFG_SYS_MPC85xx_SERDES2_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES2_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
@@ -2639,14 +2639,14 @@ struct ccsr_pman {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB1_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB2_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
+#define CFG_SYS_MPC85xx_USB1_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_OFFSET)
+#define CFG_SYS_MPC85xx_USB2_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_OFFSET)
+#define CFG_SYS_MPC85xx_USB1_PHY_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_PHY_OFFSET)
+#define CFG_SYS_MPC85xx_USB2_PHY_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_PHY_OFFSET)
 #define CONFIG_SYS_FSL_SEC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
 #define CONFIG_SYS_FSL_JR0_ADDR \
@@ -2663,17 +2663,17 @@ struct ccsr_pman {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
 
 #define CONFIG_SYS_PCI1_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI1_OFFSET)
 #define CONFIG_SYS_PCI2_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI2_OFFSET)
 #define CONFIG_SYS_PCIE1_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET)
 #define CONFIG_SYS_PCIE2_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET)
 #define CONFIG_SYS_PCIE3_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE3_OFFSET)
 #define CONFIG_SYS_PCIE4_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE4_OFFSET)
 
 #define CONFIG_SYS_SFP_ADDR  \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
@@ -2752,9 +2752,9 @@ struct dcsr_dcfg_regs {
 	u8  res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
 };
 
-#define CONFIG_SYS_MPC85xx_SCFG \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
-#define CONFIG_SYS_MPC85xx_SCFG_OFFSET	0xfc000
+#define CFG_SYS_MPC85xx_SCFG \
+	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SCFG_OFFSET)
+#define CFG_SYS_MPC85xx_SCFG_OFFSET	0xfc000
 /* The supplement configuration unit register */
 struct ccsr_scfg {
 	u32 dpslpcr;	/* 0x000 Deep Sleep Control register */
diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h
index feebe15cac..0ed6beca38 100644
--- a/arch/powerpc/include/asm/mpc85xx_gpio.h
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -20,7 +20,7 @@
 static inline void mpc85xx_gpio_set(unsigned int mask,
 		unsigned int dir, unsigned int val)
 {
-	ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
 
 	/* First mask off the unwanted parts of "dir" and "val" */
 	dir &= mask;
@@ -56,7 +56,7 @@ static inline void mpc85xx_gpio_set_high(unsigned int gpios)
 
 static inline unsigned int mpc85xx_gpio_get(unsigned int mask)
 {
-	ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
 
 	/* Read the requested values */
 	return in_be32(&gpio->gpdat) & mask;