summaryrefslogtreecommitdiff
path: root/arch/powerpc/include
diff options
context:
space:
mode:
authorValentin Longchamp <valentin.longchamp@keymile.com>2013-10-18 11:47:20 +0200
committerYork Sun <yorksun@freescale.com>2013-10-24 09:35:52 -0700
commit7e157b0ade85282a76db27cbf0ab8a2370d4d7b6 (patch)
tree85eb9638e349fc764f0733458df6d56a123edfb0 /arch/powerpc/include
parent0778bbe2d42dade68350d14a6314cfff1f4ba939 (diff)
mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it
If the DDR3 module supports industrial temperature range and requires the x2 refresh rate for that temp range, the refresh period must be 3.9us instead of 7.8 us. This was successfuly tested on kmp204x board with some MT41K128M16 DDR3 RAM chips (no module used, chips directly soldered on board with an SPD EEPROM). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix minor conflicts in fsl_ddr_dimm_params.h, lc_common_dimm_params.c, common_timing_params.h] Acked-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/fsl_ddr_dimm_params.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
index 2cad6e28578..99a72bc6e16 100644
--- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
+++ b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
@@ -78,6 +78,7 @@ typedef struct dimm_params_s {
unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
unsigned int refresh_rate_ps;
+ unsigned int extended_op_srt;
/* DDR3 doesn't need these as below */
unsigned int tis_ps; /* byte 32, spd->ca_setup */