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authorShaohui Xie <Shaohui.Xie@freescale.com>2014-06-27 14:39:31 +0800
committerYork Sun <yorksun@freescale.com>2014-07-22 16:25:55 -0700
commite55782ecccadc196a4f9d8e5e8b456e200ea9727 (patch)
tree3d4dcbee135b3765763fb876e02a6e34299502e9 /arch/powerpc/include/asm
parent3d75ec95f57224995210db5c5dea8d458cf862fb (diff)
powerpc/t4240qds: fix offset of serdes when checking reference clock
T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/include/asm')
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 8258ab38050..dfb370e051b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2905,6 +2905,8 @@ struct ccsr_sfp_regs {
#endif
#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
+#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
+#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
@@ -3090,6 +3092,10 @@ struct ccsr_sfp_regs {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
#define CONFIG_SYS_MPC85xx_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
#define CONFIG_SYS_MPC85xx_USB2_ADDR \