diff options
author | Madalin Bucur <madalin.bucur@oss.nxp.com> | 2020-04-30 16:00:03 +0300 |
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committer | Priyanka Jain <priyanka.jain@nxp.com> | 2020-06-04 18:53:20 +0530 |
commit | eb3c194c406274499b386aa67902020ca865d89d (patch) | |
tree | e55e5819b96cde0e2ff6b9a5422bbd42072b36d1 /arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi | |
parent | 37fa0b07b479eda3c7508e184233477ec5563e0f (diff) |
powerpc: dts: add QorIQ DPAA 1 FMan v3 device tree nodes
Add the QorIQ DPAA Frame Manager version 3 device tree nodes
description. The device tree fragments are copied over with little
modification from the Linux kernel source code.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi')
-rw-r--r-- | arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi new file mode 100644 index 00000000000..239c56ad1f6 --- /dev/null +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x500000 ] + * + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2020 NXP + * + */ + +fman@500000 { + fman1_rx_0x09: port@89000 { + cell-index = <0x9>; + compatible = "fsl,fman-v3-port-rx"; + reg = <0x89000 0x1000>; + }; + + fman1_tx_0x29: port@a9000 { + cell-index = <0x29>; + compatible = "fsl,fman-v3-port-tx"; + reg = <0xa9000 0x1000>; + }; + + ethernet@e2000 { + cell-index = <1>; + compatible = "fsl,fman-memac"; + reg = <0xe2000 0x1000>; + fsl,fman-ports = <&fman1_rx_0x09 &fman1_tx_0x29>; + ptp-timer = <&ptp_timer1>; + pcsphy-handle = <&pcsphy9>; + }; + + mdio@e3000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; + reg = <0xe3000 0x1000>; + fsl,erratum-a011043; /* must ignore read errors */ + + pcsphy9: ethernet-phy@0 { + reg = <0x0>; + }; + }; +}; |