diff options
| author | Matthias Fuchs <matthias.fuchs@esd.eu> | 2013-08-07 12:10:38 +0200 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-08-20 11:35:24 -0400 |
| commit | 3fb858891273945ce2238e6d4dac3363a1fb0853 (patch) | |
| tree | ee86943cebf490244fed648f69425438c3c39b95 /arch/powerpc/cpu/ppc4xx/4xx_uart.c | |
| parent | fb8f4fd3af6602320525894964ea5acd42fe51b8 (diff) | |
ppc4xx: Remove support for PPC405CR CPUs
This patch removes support for the APM 405CR CPU.
This CPU is EOL and no board uses this chip.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Diffstat (limited to 'arch/powerpc/cpu/ppc4xx/4xx_uart.c')
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/4xx_uart.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_uart.c b/arch/powerpc/cpu/ppc4xx/4xx_uart.c index cad61f3e7c..50c28a0d39 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_uart.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_uart.c @@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ +#if defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) || defined(CONFIG_440) @@ -68,7 +68,7 @@ DECLARE_GLOBAL_DATA_PTR; #define UDIV_SUBTRACT 0 #define UART0_SDR SDR0_UART0 #define UART1_SDR SDR0_UART1 -#else /* CONFIG_405GP || CONFIG_405CR */ +#else /* CONFIG_405GP */ #define CR0_MASK 0x00001fff #define CR0_EXTCLK_ENA 0x000000c0 #define CR0_UDIV_POS 1 @@ -173,7 +173,7 @@ int get_serial_clock(void) * Let's handle this in some #ifdef's for the SoC's. */ -#if defined(CONFIG_405CR) || defined(CONFIG_405GP) +#if defined(CONFIG_405GP) reg = mfdcr(CPC0_CR0) & ~CR0_MASK; #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK clk = CONFIG_SYS_EXT_SERIAL_CLOCK; @@ -200,7 +200,7 @@ int get_serial_clock(void) #else clk = CONFIG_SYS_BASE_BAUD * 16; #endif -#endif /* CONFIG_405CR */ +#endif #if defined(CONFIG_405EP) { @@ -265,4 +265,4 @@ int get_serial_clock(void) return clk; } -#endif /* CONFIG_405GP || CONFIG_405CR */ +#endif /* CONFIG_405GP */ |