diff options
| author | Minkyu Kang <mk7.kang@samsung.com> | 2012-12-10 13:44:41 +0900 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2012-12-10 14:13:27 +0900 |
| commit | 2c601c7208713ba9b2158c57adcf515f4bdbc212 (patch) | |
| tree | 9f6e70f33565beceb956b98c261bee19731d50d2 /arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | |
| parent | b8a7c467960ffb4d5a5e1eef5f7783fb6f594542 (diff) | |
| parent | fd4d564b3c80b111f18c93adb14233a6a7ddb0e9 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot into resolve
Conflicts:
README
board/samsung/universal_c210/universal.c
drivers/misc/Makefile
drivers/power/power_fsl.c
include/configs/mx35pdk.h
include/configs/mx53loco.h
include/configs/seaboard.h
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 7f466ac6a94..5495dc59eef 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -714,9 +714,13 @@ void fsl_serdes_init(void) #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 /* - * Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for - * each of the SerDes lanes selected as SGMII, XAUI, SRIO, or - * AURORA before the device is initialized. + * Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1 + * for each of the SerDes lanes selected as SGMII, XAUI, SRIO, + * or AURORA before the device is initialized. + * + * Note that this part of the SERDES-9 work-around is + * redundant if the work-around for A-4580 has already been + * applied via PBI. */ switch (lane_prtcl) { case SGMII_FM1_DTSEC1: @@ -733,10 +737,12 @@ void fsl_serdes_init(void) case SRIO1: case SRIO2: case AURORA: - clrsetbits_be32(&srds_regs->lane[idx].ttlcr0, - SRDS_TTLCR0_FLT_SEL_MASK, - SRDS_TTLCR0_FLT_SEL_750PPM | - SRDS_TTLCR0_PM_DIS); + out_be32(&srds_regs->lane[idx].ttlcr0, + SRDS_TTLCR0_FLT_SEL_KFR_26 | + SRDS_TTLCR0_FLT_SEL_KPH_28 | + SRDS_TTLCR0_FLT_SEL_750PPM | + SRDS_TTLCR0_FREQOVD_EN); + break; default: break; } |