diff options
| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:26 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:29 -0500 |
| commit | a1d558a20f1eaeae9927abc4e0978725d33bae53 (patch) | |
| tree | 3af577ebb7be24efd3c23d7a8559512d2f9bfa70 /arch/powerpc/cpu/mpc85xx/ddr-gen3.c | |
| parent | eb5394120643922626f18e5fe7b0b3dc0ed43b9a (diff) | |
powerpc/mpc85xx: Add workaround for DDR erratum A004934
After DDR controller is enabled, it performs a calibration for the
transmit data vs DQS paths. During this calibration, the DDR controller
may make an inaccurate calculation, resulting in a non-optimal tap point.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/ddr-gen3.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index 8bed5fe925b..21840bfc2a8 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -140,6 +140,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->debug[i], regs->debug[i]); } } +#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934 + out_be32(&ddr->debug[28], 0x00003000); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474 out_be32(&ddr->debug[12], 0x00000015); |