diff options
| author | Kumar Gala <galak@kernel.crashing.org> | 2011-07-21 00:20:21 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-07-29 08:53:38 -0500 |
| commit | acf3f8da98fdd432a7b0bbcc8c94d706f1bb5c72 (patch) | |
| tree | 85681bacc33dff6bfcd9f40ad2e93c9635dc4ba1 /arch/powerpc/cpu/mpc85xx/cpu_init.c | |
| parent | db564bccefaa537b4a2bd46778b00536bab17258 (diff) | |
powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E
The P2040/P2040E have no L2 cache. So we utilize the SVR to determine
if we are one of these devices and skip the L2 init code in cpu_init.c
and release. For the device tree we skip the updating of the L2 cache
properties but we still update the chain of caches so the CPC/L3 node
can be properly updated.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/cpu_init.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index f1f80f7ae4f..6aca166a98e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -392,6 +392,12 @@ int cpu_init_r(void) puts("enabled\n"); } #elif defined(CONFIG_BACKSIDE_L2_CACHE) + if ((SVR_SOC_VER(get_svr()) == SVR_P2040) || + (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) { + puts("N/A\n"); + goto skip_l2; + } + u32 l2cfg0 = mfspr(SPRN_L2CFG0); /* invalidate the L2 cache */ @@ -412,6 +418,8 @@ int cpu_init_r(void) ; printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); } + +skip_l2: #else puts("disabled\n"); #endif |