diff options
| author | Mingkai Hu <Mingkai.Hu@freescale.com> | 2013-07-04 17:30:36 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-09 12:41:42 -0700 |
| commit | 3b75e98273532ed0135846345e367ac4992b1a51 (patch) | |
| tree | a96164c4a232b07e00c921eccfe75a9f4b7b5b92 /arch/powerpc/cpu/mpc85xx/Makefile | |
| parent | 1218f7eb118fcb1ad66467b1392f05745b4e7c49 (diff) | |
powerpc/85xx: Add C29x SoC support
The Freescale C29x family is a high performance crypto co-processor.
It combines a single e500v2 core with necessary SEC engine. There're
three SoC types(C291, C292, C293) with the following features:
- 512K L2 Cache/SRAM and 512 KB platform SRAM
- DDR3/DDR3L 32bit DDR controller
- One PCI express (x1, x2, x4) Gen 2.0 Controller
- Trust Architecture 2.0
- SEC6.0 engine
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Po Liu <Po.Liu@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/Makefile')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/Makefile | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 0d1e8f1f0a..f70f0d747d 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -46,6 +46,7 @@ COBJS-$(CONFIG_MPC8568) += ddr-gen2.o COBJS-$(CONFIG_MPC8544) += ddr-gen2.o # supports ddr1/2/3 +COBJS-$(CONFIG_PPC_C29X) += ddr-gen3.o COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o COBJS-$(CONFIG_MPC8569) += ddr-gen3.o @@ -100,6 +101,7 @@ COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o # SoC specific SERDES support +COBJS-$(CONFIG_PPC_C29X) += c29x_serdes.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS-$(CONFIG_MPC8544) += mpc8544_serdes.o COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o |