diff options
| author | Tom Rini <trini@konsulko.com> | 2021-08-26 11:47:59 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-08-31 17:47:49 -0400 |
| commit | ab92b38a0161f0d8efa1c2112d944ef8f755dfbe (patch) | |
| tree | f4413fb22813b940ce12ca5079c67c7149ade8e3 /arch/powerpc/cpu/mpc85xx/Kconfig | |
| parent | e4ddf14305b28e788e09a9b1b5b2b2474234eb91 (diff) | |
Finish converting CONFIG_SYS_CACHELINE_SIZE to Kconfig
We move the SYS_CACHE_SHIFT_N options from arch/arm/Kconfig to
arch/Kconfig, and introduce SYS_CACHE_SHIFT_4 to provide a size of 16.
Introduce select statements for other architectures based on current
usage. For MIPS, we take the existing arch-specific symbol and migrate
to the generic symbol. This lets us remove a little bit of otherwise
unused code.
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Anup Patel <anup.patel@wdc.com>
Cc: Atish Patra <atish.patra@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Leo <ycliang@andestech.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/Kconfig')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/Kconfig | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index cbc8ba8d5a..cc2e4ff647 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -48,6 +48,7 @@ config TARGET_MPC8548CDS bool "Support MPC8548CDS" select ARCH_MPC8548 select FSL_VIA + select SYS_CACHE_SHIFT_5 config TARGET_P1010RDB_PA bool "Support P1010RDB_PA" @@ -322,6 +323,7 @@ config ARCH_MPC8540 config ARCH_MPC8544 bool select FSL_LAW + select SYS_CACHE_SHIFT_5 select SYS_FSL_ERRATUM_A005125 select FSL_PCIE_RESET select SYS_FSL_HAS_DDR2 @@ -356,6 +358,7 @@ config ARCH_MPC8560 config ARCH_P1010 bool select FSL_LAW + select SYS_CACHE_SHIFT_5 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 @@ -401,6 +404,7 @@ config ARCH_P1011 config ARCH_P1020 bool select FSL_LAW + select SYS_CACHE_SHIFT_5 select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ELBC_A001 @@ -496,6 +500,7 @@ config ARCH_P1025 config ARCH_P2020 bool select FSL_LAW + select SYS_CACHE_SHIFT_5 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 @@ -516,6 +521,7 @@ config ARCH_P2041 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004849 select SYS_FSL_ERRATUM_A005275 @@ -540,6 +546,7 @@ config ARCH_P3041 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004849 @@ -569,6 +576,7 @@ config ARCH_P4080 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004580 @@ -607,6 +615,7 @@ config ARCH_P5040 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004699 @@ -630,11 +639,13 @@ config ARCH_P5040 config ARCH_QEMU_E500 bool + select SYS_CACHE_SHIFT_5 config ARCH_T1024 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008109 @@ -657,6 +668,7 @@ config ARCH_T1040 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008378 @@ -679,6 +691,7 @@ config ARCH_T1042 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008378 @@ -702,6 +715,7 @@ config ARCH_T2080 select E500MC select E6500 select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 @@ -731,6 +745,7 @@ config ARCH_T4240 select E500MC select E6500 select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004468 select SYS_FSL_ERRATUM_A005871 |