diff options
| author | rick <rick@andestech.com> | 2017-05-18 14:37:53 +0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2017-05-22 14:05:46 +0800 |
| commit | b841b6e94662b3b21a56d6ecaab64dcdfb0d311c (patch) | |
| tree | 92847f53ffaeb104754e2940b32b981314627750 /arch/nds32/include/asm/cache.h | |
| parent | f5076f869855045e527de7f1367c65f55a2b1448 (diff) | |
nds32: Support AE3XX platform.
Support Andestech AE3xx platform: serial, timer device tree flow.
Signed-off-by: rick <rick@andestech.com>
Diffstat (limited to 'arch/nds32/include/asm/cache.h')
| -rw-r--r-- | arch/nds32/include/asm/cache.h | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h index 9038821b48a..7e9aac80ff6 100644 --- a/arch/nds32/include/asm/cache.h +++ b/arch/nds32/include/asm/cache.h @@ -16,6 +16,7 @@ void icache_disable(void); int dcache_status(void); void dcache_enable(void); void dcache_disable(void); +void cache_flush(void); #define DEFINE_GET_SYS_REG(reg) \ static inline unsigned long GET_##reg(void) \ @@ -30,10 +31,24 @@ void dcache_disable(void); enum cache_t {ICACHE, DCACHE}; DEFINE_GET_SYS_REG(ICM_CFG); DEFINE_GET_SYS_REG(DCM_CFG); -#define ICM_CFG_OFF_ISZ 6 /* I-cache line size */ -#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ) -#define DCM_CFG_OFF_DSZ 6 /* D-cache line size */ -#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ) +/* I-cache sets (# of cache lines) per way */ +#define ICM_CFG_OFF_ISET 0 +/* I-cache ways */ +#define ICM_CFG_OFF_IWAY 3 +#define ICM_CFG_MSK_ISET (0x7 << ICM_CFG_OFF_ISET) +#define ICM_CFG_MSK_IWAY (0x7 << ICM_CFG_OFF_IWAY) +/* D-cache sets (# of cache lines) per way */ +#define DCM_CFG_OFF_DSET 0 +/* D-cache ways */ +#define DCM_CFG_OFF_DWAY 3 +#define DCM_CFG_MSK_DSET (0x7 << DCM_CFG_OFF_DSET) +#define DCM_CFG_MSK_DWAY (0x7 << DCM_CFG_OFF_DWAY) +/* I-cache line size */ +#define ICM_CFG_OFF_ISZ 6 +#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ) +/* D-cache line size */ +#define DCM_CFG_OFF_DSZ 6 +#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ) /* * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes. |