mips: mtmips: add SPL support

This patch adds SPL support for mtmips platform. The lowlevel architecture
is split into SPL and the rest parts are built into a memory loadable
u-boot image. Optional SPL_DM and OF_CONTROL are also supported.

The increment of size is very small (< 10 KiB) if SPL_DM and OF_CONTROL are
not enabled and the memory bootable u-boot (u-boot.img) is generated
automatically so there is not need to add a separate config for it.

A lzma compressed payload (u-boot-lzma.img) is also generated and it will
be combined with u-boot-spl.bin to form the unified ROM bootable binary
u-boot-mtmips.bin.

A spl loader is added to support uncompress the payload.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

6 files changed, 120 insertions, 0 deletions

diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig
index 3f25de8b85..83d764835a 100644
--- a/arch/mips/mach-mtmips/Kconfig
+++ b/arch/mips/mach-mtmips/Kconfig
@@ -20,8 +20,18 @@ config SYS_ICACHE_LINE_SIZE
 	default 32
 
 config SYS_TEXT_BASE
+	default 0x9c000000 if !SPL
+	default 0x80200000 if SPL
+
+config SPL_TEXT_BASE
 	default 0x9c000000
 
+config SPL_PAYLOAD
+	default "u-boot-lzma.img" if SPL_LZMA
+
+config BUILD_TARGET
+	default "u-boot-with-spl.bin" if SPL
+
 choice
 	prompt "MediaTek MIPS SoC select"
 
@@ -34,6 +44,15 @@ config SOC_MT7628
 	select PINCTRL_MT7628
 	select MTK_SERIAL
 	select SYSRESET_RESETCTL
+	select SPL_SEPARATE_BSS if SPL
+	select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL
+	select SPL_LOADER_SUPPORT if SPL
+	select SPL_OF_CONTROL if SPL_DM
+	select SPL_SIMPLE_BUS if SPL_DM
+	select SPL_DM_SERIAL if SPL_DM
+	select SPL_CLK if SPL_DM && SPL_SERIAL_SUPPORT
+	select SPL_SYSRESET if SPL_DM
+	select SPL_OF_LIBFDT if SPL_OF_CONTROL
 	help
 	  This supports MediaTek MT7628/MT7688.
 
@@ -88,6 +107,14 @@ endchoice
 config SUPPORTS_BOOT_RAM
 	bool
 
+config SPL_UART2_SPIS_PINMUX
+	bool "Use alternative pinmux for UART2 in SPL stage"
+	depends on SPL_SERIAL_SUPPORT
+	default n
+	help
+	  Select this if the UART2 of your board is connected to GPIO 16/17
+	  (shared with SPIS) rather than the usual GPIO 20/21.
+
 source "board/gardena/smart-gateway-mt7688/Kconfig"
 source "board/seeed/linkit-smart-7688/Kconfig"
 
diff --git a/arch/mips/mach-mtmips/Makefile b/arch/mips/mach-mtmips/Makefile
index 72f0369030..a7e6a66304 100644
--- a/arch/mips/mach-mtmips/Makefile
+++ b/arch/mips/mach-mtmips/Makefile
@@ -3,5 +3,6 @@
 obj-y += cpu.o
 obj-y += ddr_init.o
 obj-y += ddr_cal.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
 
 obj-$(CONFIG_SOC_MT7628) += mt7628/
diff --git a/arch/mips/mach-mtmips/include/mach/serial.h b/arch/mips/mach-mtmips/include/mach/serial.h
new file mode 100644
index 0000000000..bfa246b428
--- /dev/null
+++ b/arch/mips/mach-mtmips/include/mach/serial.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author:  Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef _MTMIPS_SERIAL_H_
+#define _MTMIPS_SERIAL_H_
+
+void mtmips_spl_serial_init(void);
+
+#endif /* _MTMIPS_SERIAL_H_ */
diff --git a/arch/mips/mach-mtmips/mt7628/Makefile b/arch/mips/mach-mtmips/mt7628/Makefile
index db62e90d77..7e139d5adf 100644
--- a/arch/mips/mach-mtmips/mt7628/Makefile
+++ b/arch/mips/mach-mtmips/mt7628/Makefile
@@ -3,3 +3,4 @@
 obj-y += lowlevel_init.o
 obj-y += init.o
 obj-y += ddr.o
+obj-$(CONFIG_SPL_BUILD) += serial.o
diff --git a/arch/mips/mach-mtmips/mt7628/serial.c b/arch/mips/mach-mtmips/mt7628/serial.c
new file mode 100644
index 0000000000..a7d324792d
--- /dev/null
+++ b/arch/mips/mach-mtmips/mt7628/serial.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author:  Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "mt7628.h"
+
+void mtmips_spl_serial_init(void)
+{
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+	void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
+
+#if CONFIG_CONS_INDEX == 1
+	clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART0_MODE_M);
+#elif CONFIG_CONS_INDEX == 2
+	clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART1_MODE_M);
+#elif CONFIG_CONS_INDEX == 3
+	setbits_32(base + SYSCTL_AGPIO_CFG_REG, EPHY_GPIO_AIO_EN_M);
+#ifdef CONFIG_SPL_UART2_SPIS_PINMUX
+	setbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M);
+	clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M,
+		      1 << UART2_MODE_S);
+#else
+	clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M);
+	clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M,
+		      1 << SPIS_MODE_S);
+#endif /* CONFIG_SPL_UART2_SPIS_PINMUX */
+#endif /* CONFIG_CONS_INDEX */
+#endif /* CONFIG_SPL_SERIAL_SUPPORT */
+}
diff --git a/arch/mips/mach-mtmips/spl.c b/arch/mips/mach-mtmips/spl.c
new file mode 100644
index 0000000000..2a24af70c3
--- /dev/null
+++ b/arch/mips/mach-mtmips/spl.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
+#include <fdt.h>
+#include <spl.h>
+#include <asm/sections.h>
+#include <linux/sizes.h>
+#include <mach/serial.h>
+
+void __noreturn board_init_f(ulong dummy)
+{
+	spl_init();
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+	/*
+	 * mtmips_spl_serial_init() is useful if debug uart is enabled,
+	 * or DM based serial is not enabled.
+	 */
+	mtmips_spl_serial_init();
+	preloader_console_init();
+#endif
+
+	board_init_r(NULL, 0);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = BOOT_DEVICE_NOR;
+}
+
+unsigned long spl_nor_get_uboot_base(void)
+{
+	void *uboot_base = __image_copy_end;
+
+	if (fdt_magic(uboot_base) == FDT_MAGIC)
+		return (unsigned long)uboot_base + fdt_totalsize(uboot_base);
+
+	return (unsigned long)uboot_base;
+}