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authorPaul Burton <paul.burton@mips.com>2017-11-21 11:18:38 -0800
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2017-11-28 21:59:30 +0100
commitd8b326976a44f185c52255458142086e0e8a7c34 (patch)
treeee2fb8c4dbaf65572e5c0cf298b190c95bd75193 /arch/mips/include/asm
parent219c2db384ffc4877c52bd58e7b55a62b663fed2 (diff)
MIPS: Clear instruction hazards in flush_cache()
When writing code, for example during relocation, we ensure that the icache has a coherent view of the new instructions with a call to flush_cache(). This handles the bulk of the work to ensure the new instructions will execute as expected, however it does not ensure that the CPU pipeline doesn't already contain instructions taken from a stale view of the affected memory. This could theoretically be a problem for relocation, but in practice typically isn't because we sync caches for enough code after the entry point of the newly written code that by the time the CPU pipeline might possibly fetch any of it we'll have long ago written it back & invalidated any stale icache entries. This is however a problem for shorter regions of code. In preparation for later patches which write shorter segments of code, ensure any instruction hazards are cleared by flush_cache() by introducing & using a new instruction_hazard_barrier() function which makes use of the jr.hb instruction to clear the hazard. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: u-boot@lists.denx.de
Diffstat (limited to 'arch/mips/include/asm')
-rw-r--r--arch/mips/include/asm/system.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
index c9c5961462..eaf1b2290d 100644
--- a/arch/mips/include/asm/system.h
+++ b/arch/mips/include/asm/system.h
@@ -14,8 +14,10 @@
#ifndef _ASM_SYSTEM_H
#define _ASM_SYSTEM_H
+#include <asm/asm.h>
#include <asm/sgidefs.h>
#include <asm/ptrace.h>
+#include <linux/stringify.h>
#if 0
#include <linux/kernel.h>
#endif
@@ -270,4 +272,15 @@ static inline void execution_hazard_barrier(void)
".set reorder");
}
+static inline void instruction_hazard_barrier(void)
+{
+ unsigned long tmp;
+
+ asm volatile(
+ __stringify(PTR_LA) "\t%0, 1f\n"
+ " jr.hb %0\n"
+ "1: .insn"
+ : "=&r"(tmp));
+}
+
#endif /* _ASM_SYSTEM_H */