diff options
| author | Paul Burton <paul.burton@imgtec.com> | 2016-09-21 11:18:54 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-09-21 15:04:04 +0200 |
| commit | 4baa0ab67d504f3b4318f999631e3f83d0c52c4a (patch) | |
| tree | 25fcdc21f993e7f305d870068cc8fd76b9508f48 /arch/mips/include/asm/global_data.h | |
| parent | b2b135d980a7171c9b0eefbb38861ccbe9a47f97 (diff) | |
MIPS: L2 cache support
This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.
If the L2 can be bypassed then we bypass it early in boot & initialise
the L1 caches first, such that we can start making use of the L1
instruction cache as early as possible. Otherwise we initialise the L2
first such that the L1s have no opportunity to generate access to the
uninitialised L2.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'arch/mips/include/asm/global_data.h')
| -rw-r--r-- | arch/mips/include/asm/global_data.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h index 8533b691b65..0078bbe1b85 100644 --- a/arch/mips/include/asm/global_data.h +++ b/arch/mips/include/asm/global_data.h @@ -25,6 +25,9 @@ struct arch_global_data { unsigned short l1i_line_size; unsigned short l1d_line_size; #endif +#ifdef CONFIG_MIPS_L2_CACHE + unsigned short l2_line_size; +#endif }; #include <asm-generic/global_data.h> |