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| author | Paul Burton <paul.burton@imgtec.com> | 2016-09-21 11:18:54 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-09-21 15:04:04 +0200 |
| commit | 4baa0ab67d504f3b4318f999631e3f83d0c52c4a (patch) | |
| tree | 25fcdc21f993e7f305d870068cc8fd76b9508f48 /arch/mips/Kconfig | |
| parent | b2b135d980a7171c9b0eefbb38861ccbe9a47f97 (diff) | |
MIPS: L2 cache support
This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.
If the L2 can be bypassed then we bypass it early in boot & initialise
the L1 caches first, such that we can start making use of the L1
instruction cache as early as possible. Otherwise we initialise the L2
first such that the L1s have no opportunity to generate access to the
uninitialised L2.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'arch/mips/Kconfig')
| -rw-r--r-- | arch/mips/Kconfig | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 47056b4bf8a..76714379a4c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -315,6 +315,12 @@ config MIPS_L1_CACHE_SHIFT default "4" if MIPS_L1_CACHE_SHIFT_4 default "5" +config MIPS_L2_CACHE + bool + help + Select this if your system includes an L2 cache and you want U-Boot + to initialise & maintain it. + config DYNAMIC_IO_PORT_BASE bool |