diff options
| author | Ovidiu Panait <ovpanait@gmail.com> | 2022-05-31 21:14:30 +0300 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2022-06-24 14:16:00 +0200 |
| commit | b195134984ec714f92632704e4725ced170ab1da (patch) | |
| tree | 72552154a552750b5c9d81ffb6645005161af08a /arch/microblaze | |
| parent | 84488fc69348367ee693ea4ab6affe3cbcae97a0 (diff) | |
microblaze: cache: introduce flush_cache_all()
All flush_cache() calls in microblaze code are supposed to flush the
entire instruction and data caches, so introduce flush_cache_all()
helper to handle this.
Also, provide implementations for flush_dcache_all() and
invalidate_icache_all() so that icache and dcache u-boot commands can
work.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-9-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'arch/microblaze')
| -rw-r--r-- | arch/microblaze/cpu/cache.c | 20 | ||||
| -rw-r--r-- | arch/microblaze/cpu/start.S | 8 | ||||
| -rw-r--r-- | arch/microblaze/include/asm/cache.h | 5 | ||||
| -rw-r--r-- | arch/microblaze/lib/bootm.c | 2 |
4 files changed, 26 insertions, 9 deletions
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c index d5c0afd935..b99b8c1706 100644 --- a/arch/microblaze/cpu/cache.c +++ b/arch/microblaze/cpu/cache.c @@ -24,6 +24,11 @@ static void __invalidate_icache(ulong addr, ulong size) } } +void invalidate_icache_all(void) +{ + __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE); +} + static void __flush_dcache(ulong addr, ulong size) { if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) { @@ -38,6 +43,11 @@ static void __flush_dcache(ulong addr, ulong size) } } +void flush_dcache_all(void) +{ + __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE); +} + int dcache_status(void) { int i = 0; @@ -65,7 +75,7 @@ void icache_enable(void) void icache_disable(void) { - __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE); + invalidate_icache_all(); MSRCLR(0x20); } @@ -77,7 +87,7 @@ void dcache_enable(void) void dcache_disable(void) { - __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE); + flush_dcache_all(); MSRCLR(0x80); } @@ -87,3 +97,9 @@ void flush_cache(ulong addr, ulong size) __invalidate_icache(addr, size); __flush_dcache(addr, size); } + +void flush_cache_all(void) +{ + invalidate_icache_all(); + flush_dcache_all(); +} diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 6e3ffafa5f..e6a30e8e00 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -98,9 +98,7 @@ uboot_sym_start: #endif /* Flush cache before enable cache */ - addik r5, r0, 0 - addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE - brlid r15, flush_cache + brlid r15, flush_cache_all nop /* enable instruction and data cache */ @@ -349,9 +347,7 @@ relocate_code: #endif /* Flush caches to ensure consistency */ - addik r5, r0, 0 - addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE - brlid r15, flush_cache + brlid r15, flush_cache_all nop 2: addi r5, r31, 0 /* gd is initialized in board_r.c */ diff --git a/arch/microblaze/include/asm/cache.h b/arch/microblaze/include/asm/cache.h index baee01a0e2..c39b66dd7d 100644 --- a/arch/microblaze/include/asm/cache.h +++ b/arch/microblaze/include/asm/cache.h @@ -18,4 +18,9 @@ #define ARCH_DMA_MINALIGN 16 #endif +/** + * flush_cache_all - flush the entire instruction/data caches + */ +void flush_cache_all(void); + #endif /* __MICROBLAZE_CACHE_H__ */ diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 48e05333a6..af946b8642 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -57,7 +57,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) "(fake run for tracing)" : ""); bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); - flush_cache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE); + flush_cache_all(); if (!fake) { /* |