diff options
| author | Simon Glass <sjg@chromium.org> | 2019-11-14 12:57:36 -0700 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-12-02 18:23:14 -0500 |
| commit | 6cc915b5fb2e3467b20735b112a7463cc77ec3c3 (patch) | |
| tree | 333c09c4aff924b1913865d5f174e47b37217220 /arch/microblaze/cpu | |
| parent | 62270f4395f86bd5231fcb9c1710e42be7d67d60 (diff) | |
arm: powerpc: Tidy up code style for cache functions
Remove the unwanted space before the bracket.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/microblaze/cpu')
| -rw-r--r-- | arch/microblaze/cpu/cache.c | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c index eebeb37830..94114555ff 100644 --- a/arch/microblaze/cpu/cache.c +++ b/arch/microblaze/cpu/cache.c @@ -8,7 +8,7 @@ #include <common.h> #include <asm/asm.h> -int dcache_status (void) +int dcache_status(void) { int i = 0; int mask = 0x80; @@ -18,7 +18,7 @@ int dcache_status (void) return i; } -int icache_status (void) +int icache_status(void) { int i = 0; int mask = 0x20; @@ -28,28 +28,32 @@ int icache_status (void) return i; } -void icache_enable (void) { +void icache_enable(void) +{ MSRSET(0x20); } -void icache_disable(void) { +void icache_disable(void) +{ /* we are not generate ICACHE size -> flush whole cache */ flush_cache(0, 32768); MSRCLR(0x20); } -void dcache_enable (void) { +void dcache_enable(void) +{ MSRSET(0x80); } -void dcache_disable(void) { +void dcache_disable(void) +{ #ifdef XILINX_USE_DCACHE flush_cache(0, XILINX_DCACHE_BYTE_SIZE); #endif MSRCLR(0x80); } -void flush_cache (ulong addr, ulong size) +void flush_cache(ulong addr, ulong size) { int i; for (i = 0; i < size; i += 4) |