diff options
| author | Tom Rini <trini@konsulko.com> | 2021-05-14 21:34:10 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-07-07 19:52:22 -0400 |
| commit | 9b7993bba939220dba945b2dbf979d2c3e68123d (patch) | |
| tree | 2744f0644fdfc06c3c81d7665c3005d95b040e0f /arch/m68k | |
| parent | eb83d10b4261a4d54e8d132e82933ce98dafb23d (diff) | |
m68k: Remove M5475x boards
These board has not been converted to CONFIG_DM_PCI by the deadline.
Remove them. As this is the last of the mcf547x_8x family of boards,
remove that support as well.
Cc: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/m68k')
25 files changed, 2 insertions, 1765 deletions
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index f7f6d08be3..cf45d789d6 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -65,12 +65,6 @@ config MCF5227x select DM_SERIAL bool -config MCF547x_8x - select OF_CONTROL - select DM - select DM_SERIAL - bool - # processor type config M5208 bool @@ -137,10 +131,6 @@ config M52277 bool select MCF5227x -config M547x - bool - select MCF547x_8x - choice prompt "Target select" optional @@ -213,10 +203,6 @@ config TARGET_M54455EVB bool "Support M54455EVB" select M54455 -config TARGET_M5475EVB - bool "Support M5475EVB" - select M547x - config TARGET_AMCORE bool "Support AMCORE" select M5307 @@ -244,7 +230,6 @@ source "board/freescale/m5373evb/Kconfig" source "board/freescale/m54418twr/Kconfig" source "board/freescale/m54451evb/Kconfig" source "board/freescale/m54455evb/Kconfig" -source "board/freescale/m547xevb/Kconfig" source "board/sysam/amcore/Kconfig" source "board/sysam/stmark2/Kconfig" diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index 7f23ff4588..86b36e1a40 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile @@ -19,14 +19,12 @@ cpuflags-$(CONFIG_MCF5301x) := -mcpu=53015 -fPIC cpuflags-$(CONFIG_MCF532x) := -mcpu=5329 -fPIC cpuflags-$(CONFIG_MCF5441x) := -mcpu=54418 -fPIC cpuflags-$(CONFIG_MCF5445x) := -mcpu=54455 -fPIC -cpuflags-$(CONFIG_MCF547x_8x) := -mcpu=5485 -fPIC PLATFORM_CPPFLAGS += $(cpuflags-y) ldflags-$(CONFIG_MCF5441x) := --got=single ldflags-$(CONFIG_MCF5445x) := --got=single -ldflags-$(CONFIG_MCF547x_8x) := --got=single ifneq (,$(findstring -linux-,$(shell $(CC) --version))) ifneq (,$(findstring GOT,$(shell $(LD) --help))) diff --git a/arch/m68k/cpu/mcf547x_8x/Makefile b/arch/m68k/cpu/mcf547x_8x/Makefile deleted file mode 100644 index 0db3386aa8..0000000000 --- a/arch/m68k/cpu/mcf547x_8x/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -# ccflags-y += -DET_DEBUG - -extra-y = start.o -obj-y = cpu.o speed.o cpu_init.o pci.o interrupts.o slicetimer.o diff --git a/arch/m68k/cpu/mcf547x_8x/cpu.c b/arch/m68k/cpu/mcf547x_8x/cpu.c deleted file mode 100644 index c1361e7057..0000000000 --- a/arch/m68k/cpu/mcf547x_8x/cpu.c +++ /dev/null @@ -1,153 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include <common.h> -#include <init.h> -#include <net.h> -#include <vsprintf.h> -#include <watchdog.h> -#include <command.h> -#include <netdev.h> -#include <asm/global_data.h> - -#include <asm/immap.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); - - out_be16(&gptmr->pre, 10); - out_be16(&gptmr->cnt, 1); - - /* enable watchdog, set timeout to 0 and wait */ - out_8(&gptmr->mode, GPT_TMS_SGPIO); - out_8(&gptmr->ctrl, GPT_CTRL_WDEN | GPT_CTRL_CE); - - /* we don't return! */ - return 1; -}; - -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo(void) -{ - siu_t *siu = (siu_t *) MMAP_SIU; - u16 id = 0; - - puts("CPU: "); - - switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) { - case 0x0C: - id = 5485; - break; - case 0x0D: - id = 5484; - break; - case 0x0E: - id = 5483; - break; - case 0x0F: - id = 5482; - break; - case 0x10: - id = 5481; - break; - case 0x11: - id = 5480; - break; - case 0x12: - id = 5475; - break; - case 0x13: - id = 5474; - break; - case 0x14: - id = 5473; - break; - case 0x15: - id = 5472; - break; - case 0x16: - id = 5471; - break; - case 0x17: - id = 5470; - break; - } - - if (id) { - char buf1[32], buf2[32]; - - printf("Freescale MCF%d\n", id); - printf(" CPU CLK %s MHz BUS CLK %s MHz\n", - strmhz(buf1, gd->cpu_clk), - strmhz(buf2, gd->bus_clk)); - } - - return 0; -}; -#endif /* CONFIG_DISPLAY_CPUINFO */ - -#if defined(CONFIG_HW_WATCHDOG) -/* Called by macro WATCHDOG_RESET */ -void hw_watchdog_reset(void) -{ - gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); - - out_8(&gptmr->ocpw, 0xa5); -} - -int watchdog_disable(void) -{ - gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); - - /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */ - out_8(&gptmr->mode, 0); - out_8(&gptmr->ctrl, 0); - - puts("WATCHDOG:disabled\n"); - - return (0); -} - -int watchdog_init(void) -{ - gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); - - out_be16(&gptmr->pre, CONFIG_WATCHDOG_TIMEOUT); - out_be16(&gptmr->cnt, CONFIG_SYS_TIMER_PRESCALER * 1000); - - out_8(&gptmr->mode, GPT_TMS_SGPIO); - out_8(&gptmr->ctrl, GPT_CTRL_CE | GPT_CTRL_WDEN); - puts("WATCHDOG:enabled\n"); - - return (0); -} -#endif /* CONFIG_HW_WATCHDOG */ - -#if defined(CONFIG_FSLDMAFEC) || defined(CONFIG_MCFFEC) -/* Default initializations for MCFFEC controllers. To override, - * create a board-specific function called: - * int board_eth_init(struct bd_info *bis) - */ - -int cpu_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FSLDMAFEC) - mcdmafec_initialize(bis); -#endif -#if defined(CONFIG_MCFFEC) - mcffec_initialize(bis); -#endif - return 0; -} -#endif diff --git a/arch/m68k/cpu/mcf547x_8x/cpu_init.c b/arch/m68k/cpu/mcf547x_8x/cpu_init.c deleted file mode 100644 index 8e42b63141..0000000000 --- a/arch/m68k/cpu/mcf547x_8x/cpu_init.c +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include <common.h> -#include <MCD_dma.h> -#include <cpu_func.h> -#include <init.h> -#include <asm/immap.h> -#include <asm/io.h> - -#if defined(CONFIG_CMD_NET) -#include <config.h> -#include <net.h> -#include <asm/fec.h> -#include <asm/fsl_mcdmafec.h> -#endif - -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f(void) -{ - gpio_t *gpio = (gpio_t *) MMAP_GPIO; - fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB; - - out_be32(&xlbarb->adrto, 0x2000); - out_be32(&xlbarb->datto, 0x2500); - out_be32(&xlbarb->busto, 0x3000); - - out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT); - - /* Master Priority Enable */ - out_be32(&xlbarb->prien, 0xff); - out_be32(&xlbarb->pri, 0); - -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); -#endif - -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); -#endif - -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); -#endif - -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); -#endif - -#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) - out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); - out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); - out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); -#endif - -#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) - out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); - out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); - out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); -#endif - -#ifdef CONFIG_SYS_I2C_FSL - out_be16(&gpio->par_feci2cirq, - GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA); -#endif - - icache_enable(); -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r(void) -{ -#if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC) - MCD_initDma((dmaRegs *) (MMAP_MCDMA), (void *)(MMAP_SRAM + 512), - MCD_RELOC_TASKS); -#endif - return (0); -} - -void uart_port_conf(int port) -{ - gpio_t *gpio = (gpio_t *) MMAP_GPIO; - u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40); - - /* Setup Ports: */ - switch (port) { - case 0: - out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0); - break; - case 1: - out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1); - break; - case 2: - out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2); - break; - case 3: - out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3); - break; - } - - clrbits_8(pscsicr, 0x07); -} - -#if defined(CONFIG_CMD_NET) -int fecpin_setclear(fec_info_t *info, int setclear) -{ - gpio_t *gpio = (gpio_t *) MMAP_GPIO; - u32 fec0_base; - - if (fec_get_base_addr(0, &fec0_base)) - return -1; - - if (setclear) { - if (info->iobase == fec0_base) - setbits_be16(&gpio->par_feci2cirq, 0xf000); - else - setbits_be16(&gpio->par_feci2cirq, 0x0fc0); - } else { - if (info->iobase == fec0_base) - clrbits_be16(&gpio->par_feci2cirq, 0xf000); - else - clrbits_be16(&gpio->par_feci2cirq, 0x0fc0); - } - return 0; -} -#endif diff --git a/arch/m68k/cpu/mcf547x_8x/interrupts.c b/arch/m68k/cpu/mcf547x_8x/interrupts.c deleted file mode 100644 index 703090ddc2..0000000000 --- a/arch/m68k/cpu/mcf547x_8x/interrupts.c +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* CPU specific interrupt routine */ -#include <common.h> -#include <irq_func.h> -#include <asm/immap.h> -#include <asm/io.h> - -int interrupt_init(void) -{ - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - - /* Make sure all interrupts are disabled */ - setbits_be32(&intp->imrh0, 0xffffffff); - setbits_be32(&intp->imrl0, 0xffffffff); - - enable_interrupts(); - - return 0; -} - -#if defined(CONFIG_SLTTMR) -void dtimer_intr_setup(void) -{ - int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - - out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); - clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); -} -#endif diff --git a/arch/m68k/cpu/mcf547x_8x/pci.c b/arch/m68k/cpu/mcf547x_8x/pci.c deleted file mode 100644 index 74ba68124f..0000000000 --- a/arch/m68k/cpu/mcf547x_8x/pci.c +++ /dev/null @@ -1,154 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* - * PCI Configuration space access support - */ -#include <common.h> -#include <pci.h> -#include <asm/io.h> -#include <asm/immap.h> -#include <linux/delay.h> - -#if defined(CONFIG_PCI) -/* System RAM mapped over PCI */ -#define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) - -#define cfg_read(val, addr, type, op) *val = op((type)(addr)); -#define cfg_write(val, addr, type, op) op((type *)(addr), (val)); - -#define PCI_OP(rw, size, type, op, mask) \ -int pci_##rw##_cfg_##size(struct pci_controller *hose, \ - pci_dev_t dev, int offset, type val) \ -{ \ - u32 addr = 0; \ - u16 cfg_type = 0; \ - addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \ - out_be32(hose->cfg_addr, addr); \ - cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ - __asm__ __volatile__("nop"); \ - __asm__ __volatile__("nop"); \ - out_be32(hose->cfg_addr, addr & 0x7fffffff); \ - return 0; \ -} - -PCI_OP(read, byte, u8 *, in_8, 3) -PCI_OP(read, word, u16 *, in_le16, 2) -PCI_OP(write, byte, u8, out_8, 3) -PCI_OP(write, word, u16, out_le16, 2) -PCI_OP(write, dword, u32, out_le32, 0) - -int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev, - int offset, u32 * val) -{ - u32 addr; - u32 tmpv; - u32 mask = 2; /* word access */ - /* Read lower 16 bits */ - addr = ((offset & 0xfc) | (dev) | 0x80000000); - out_be32(hose->cfg_addr, addr); - *val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); - __asm__ __volatile__("nop"); - out_be32(hose->cfg_addr, addr & 0x7fffffff); - - /* Read upper 16 bits */ - offset += 2; - addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000); - out_be32(hose->cfg_addr, addr); - tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); - __asm__ __volatile__("nop"); - out_be32(hose->cfg_addr, addr & 0x7fffffff); - - /* combine results into dword value */ - *val = (tmpv << 16) | *val; - - return 0; -} - -void pci_mcf547x_8x_init(struct pci_controller *hose) -{ - pci_t *pci = (pci_t *) MMAP_PCI; - gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - /* Port configuration */ - out_be16(&gpio->par_pcibg, - GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) | - GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) | - GPIO_PAR_PCIBG_PCIBG4(3)); - out_be16(&gpio->par_pcibr, - GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) | - GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) | - GPIO_PAR_PCIBR_PCIBR4(3)); - - /* Assert reset bit */ - setbits_be32(&pci->gscr, PCI_GSCR_PR); - - out_be32(&pci->tcr1, PCI_TCR1_P); - - /* Initiator windows */ - out_be32(&pci->iw0btar, - CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16)); - out_be32(&pci->iw1btar, - CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16)); - out_be32(&pci->iw2btar, - CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16)); - - out_be32(&pci->iwcr, - PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | - PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO); - - out_be32(&pci->icr, 0); - - /* Enable bus master and mem access */ - out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M); - - /* Cache line size and master latency */ - out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xf8)); - out_be32(&pci->cr2, 0); - -#ifdef CONFIG_SYS_PCI_BAR0 - out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0)); - out_be32(&pci->tbatr0a, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN); -#endif -#ifdef CONFIG_SYS_PCI_BAR1 - out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1)); - out_be32(&pci->tbatr1a, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN); -#endif - - /* Deassert reset bit */ - clrbits_be32(&pci->gscr, PCI_GSCR_PR); - udelay(1000); - - /* Enable PCI bus master support */ - hose->first_busno = 0; - hose->last_busno = 0xff; - - pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS, - CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM); - - pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS, - CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); - - pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS, - CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose->region_count = 3; - - hose->cfg_addr = &(pci->car); - hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS; - - pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word, - pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word, - pci_write_cfg_dword); - - /* Hose scan */ - pci_register_hose(hose); - hose->last_busno = pci_hose_scan(hose); -} -#endif /* CONFIG_PCI */ diff --git a/arch/m68k/cpu/mcf547x_8x/slicetimer.c b/arch/m68k/cpu/mcf547x_8x/slicetimer.c deleted file mode 100644 index dc076fc6e8..0000000000 --- a/arch/m68k/cpu/mcf547x_8x/slicetimer.c +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include <common.h> -#include <init.h> -#include <irq_func.h> -#include <asm/global_data.h> -#include <linux/delay.h> - -#include <asm/timer.h> -#include <asm/immap.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -static ulong timestamp; - -#if defined(CONFIG_SLTTMR) -#ifndef CONFIG_SYS_UDELAY_BASE -# error "uDelay base not defined!" -#endif - -#if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK) -# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!" -#endif -extern void dtimer_intr_setup(void); - -void __udelay(unsigned long usec) -{ - slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE); - u32 now, freq; - - /* 1 us period */ - freq = CONFIG_SYS_TIMER_PRESCALER; - - /* Disable */ - out_be32(&timerp->cr, 0); - out_be32(&timerp->tcnt, usec * freq); - out_be32(&timerp->cr, SLT_CR_TEN); - - now = in_be32(&timerp->cnt); - while (now != 0) - now = in_be32(&timerp->cnt); - - setbits_be32(&timerp->sr, SLT_SR_ST); - out_be32(&timerp->cr, 0); -} - -void dtimer_interrupt(void *not_used) -{ - slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE); - - /* check for timer interrupt asserted */ - if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) { - setbits_be32(&timerp->sr, SLT_SR_ST); - timestamp++; - return; - } -} - -int timer_init(void) -{ - slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE); - - timestamp = 0; - - /* disable timer */ - out_be32(&timerp->cr, 0); - out_be32(&timerp->tcnt, 0); - /* clear status */ - out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST); - - /* initialize and enable timer interrupt */ - irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0); - - /* Interrupt every ms */ - out_be32(&timerp->tcnt, 1000 * CONFIG_SYS_TIMER_PRESCALER); - - dtimer_intr_setup(); - - /* set a period of 1us, set timer mode to restart and - enable timer and interrupt */ - out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN); - return 0; -} - -ulong get_timer(ulong base) -{ - return (timestamp - base); -} - -#endif /* CONFIG_SLTTMR */ diff --git a/arch/m68k/cpu/mcf547x_8x/speed.c b/arch/m68k/cpu/mcf547x_8x/speed.c deleted file mode 100644 index bbcf601f38..0000000000 --- a/arch/m68k/cpu/mcf547x_8x/speed.c +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include <common.h> -#include <clock_legacy.h> -#include <asm/global_data.h> -#include <asm/processor.h> - -#include <asm/immap.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * get_clocks() fills in gd->cpu_clock and gd->bus_clk - */ -int get_clocks(void) -{ - gd->bus_clk = CONFIG_SYS_CLK; - gd->cpu_clk = (gd->bus_clk * 2); - -#ifdef CONFIG_SYS_I2C_FSL - gd->arch.i2c1_clk = gd->bus_clk; -#endif - - return (0); -} diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S deleted file mode 100644 index b70842b2b8..0000000000 --- a/arch/m68k/cpu/mcf547x_8x/start.S +++ /dev/null @@ -1,264 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de> - * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com> - */ - -#include <asm-offsets.h> -#include <config.h> -#include "version.h" -#include <asm/cache.h> - -#define _START _start -#define _FAULT _fault - -#define SAVE_ALL \ - move.w #0x2700,%sr; /* disable intrs */ \ - subl #60,%sp; /* space for 15 regs */ \ - moveml %d0-%d7/%a0-%a6,%sp@; - -#define RESTORE_ALL \ - moveml %sp@,%d0-%d7/%a0-%a6; \ - addl #60,%sp; /* space for 15 regs */ \ - rte; - -.text - -/* - * Vector table. This is used for initial platform startup. - * These vectors are to catch any un-intended traps. - */ -_vectors: -INITSP: .long 0x00000000 /* Initial SP */ -INITPC: .long _START /* Initial PC */ - -vector02_0F: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -/* Reserved */ -vector10_17: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector18_1F: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -/* TRAP #0 - #15 */ -vector20_2F: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -/* Reserved */ -vector30_3F: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector64_127: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector128_191: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -vector192_255: -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - -.text - -.globl _start -_start: - nop - nop - move.w #0x2700,%sr /* Mask off Interrupt */ - - /* Set vector base register at the beginning of the Flash */ - move.l #CONFIG_SYS_FLASH_BASE, %d0 - movec %d0, %VBR - - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 - movec %d0, %RAMBAR0 - - move.l #(CONFIG_SYS_INIT_RAM1_ADDR + CONFIG_SYS_INIT_RAM1_CTRL), %d0 - movec %d0, %RAMBAR1 - - move.l #CONFIG_SYS_MBAR, %d0 /* set MBAR address */ - move.c %d0, %MBAR - - /* invalidate and disable cache */ - move.l #0x01040100, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0, %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 - movec %d0, %ACR2 - movec %d0, %ACR3 - - /* initialize general use internal ram */ - move.l #0, %d0 - move.l #(ICACHE_STATUS), %a1 /* icache */ - move.l #(DCACHE_STATUS), %a2 /* icache */ - move.l %d0, (%a1) - move.l %d0, (%a2) - - /* put relocation table address to a5 */ - move.l #__got_start, %a5 - - /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp - - /* - * if configured, malloc_f arena will be reserved first, - * then (and always) gd struct space will be reserved - */ - move.l %sp, -(%sp) - move.l #board_init_f_alloc_reserve, %a1 - jsr (%a1) - - /* update stack and frame-pointers */ - move.l %d0, %sp - move.l %sp, %fp - - /* initialize reserved area */ - move.l %d0, -(%sp) - move.l #board_init_f_init_reserve, %a1 - jsr (%a1) - - /* run low-level CPU init code (from flash) */ - jbsr cpu_init_f - - /* run low-level board init code (from flash) */ - clr.l %sp@- - jbsr board_init_f - - /* board_init_f() does not return */ - -/******************************************************************************/ - -/* - * void relocate_code(addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r3 = dest - * r4 = src - * r5 = length in bytes - * r6 = cachelinesize - */ -.globl relocate_code -relocate_code: - link.w %a6,#0 - move.l 8(%a6), %sp /* set new stack pointer */ - - move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ - move.l 16(%a6), %a0 /* Save copy of Destination Address */ - - move.l #CONFIG_SYS_MONITOR_BASE, %a1 - move.l #__init_end, %a2 - move.l %a0, %a3 - - /* copy the code to RAM */ -1: - move.l (%a1)+, (%a3)+ - cmp.l %a1,%a2 - bgt.s 1b - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - move.l %a0, %a1 - add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 - jmp (%a1) - -in_ram: - -clear_bss: - /* - * Now clear BSS segment - */ - move.l %a0, %a1 - add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a0, %d1 - add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 -6: - clr.l (%a1)+ - cmp.l %a1,%d1 - bgt.s 6b - - /* - * fix got table in RAM - */ - move.l %a0, %a1 - add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a1,%a5 /* fix got pointer register a5 */ - - move.l %a0, %a2 - add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 - -7: - move.l (%a1),%d1 - sub.l #_start,%d1 - add.l %a0,%d1 - move.l %d1,(%a1)+ - cmp.l %a2, %a1 - bne 7b - - /* calculate relative jump to board_init_r in ram */ - move.l %a0, %a1 - add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 - - /* set parameters for board_init_r */ - move.l %a0,-(%sp) /* dest_addr */ - move.l %d0,-(%sp) /* gd */ - jsr (%a1) - -/******************************************************************************/ - -/* exception code */ -.globl _fault -_fault: - bra _fault - -.globl _exc_handler -_exc_handler: - SAVE_ALL - movel %sp,%sp@- - bsr exc_handler - addql #4,%sp - RESTORE_ALL - -.globl _int_handler -_int_handler: - SAVE_ALL - movel %sp,%sp@- - bsr int_handler - addql #4,%sp - RESTORE_ALL - -/******************************************************************************/ - -.globl version_string -version_string: -.ascii U_BOOT_VERSION_STRING, "\0" -.align 4 diff --git a/arch/m68k/dts/M5475AFE.dts b/arch/m68k/dts/M5475AFE.dts deleted file mode 100644 index 7895b520cf..0000000000 --- a/arch/m68k/dts/M5475AFE.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> - */ - -/dts-v1/; -/include/ "mcf54xx.dtsi" - -/ { - model = "Freescale M5475AFE"; - compatible = "fsl,M5475AFE"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; - mii-base = <0>; -}; diff --git a/arch/m68k/dts/M5475BFE.dts b/arch/m68k/dts/M5475BFE.dts deleted file mode 100644 index ffbc2d6a06..0000000000 --- a/arch/m68k/dts/M5475BFE.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> - */ - -/dts-v1/; -/include/ "mcf54xx.dtsi" - -/ { - model = "Freescale M5475BFE"; - compatible = "fsl,M5475BFE"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; - mii-base = <0>; -}; diff --git a/arch/m68k/dts/M5475CFE.dts b/arch/m68k/dts/M5475CFE.dts deleted file mode 100644 index f1033f7efb..0000000000 --- a/arch/m68k/dts/M5475CFE.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> - */ - -/dts-v1/; -/include/ "mcf54xx.dtsi" - -/ { - model = "Freescale M5475CFE"; - compatible = "fsl,M5475CFE"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; - mii-base = <0>; -}; diff --git a/arch/m68k/dts/M5475DFE.dts b/arch/m68k/dts/M5475DFE.dts deleted file mode 100644 index 69a8faba83..0000000000 --- a/arch/m68k/dts/M5475DFE.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> - */ - -/dts-v1/; -/include/ "mcf54xx.dtsi" - -/ { - model = "Freescale M5475DFE"; - compatible = "fsl,M5475DFE"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; - mii-base = <0>; -}; diff --git a/arch/m68k/dts/M5475EFE.dts b/arch/m68k/dts/M5475EFE.dts deleted file mode 100644 index 3c898958c8..0000000000 --- a/arch/m68k/dts/M5475EFE.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> - */ - -/dts-v1/; -/include/ "mcf54xx.dtsi" - -/ { - model = "Freescale M5475EFE"; - compatible = "fsl,M5475EFE"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; - mii-base = <0>; -}; diff --git a/arch/m68k/dts/M5475FFE.dts b/arch/m68k/dts/M5475FFE.dts deleted file mode 100644 index bb3c21588f..0000000000 --- a/arch/m68k/dts/M5475FFE.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> - */ - -/dts-v1/; -/include/ "mcf54xx.dtsi" - -/ { - model = "Freescale M5475FFE"; - compatible = "fsl,M5475FFE"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; - mii-base = <0>; -}; diff --git a/arch/m68k/dts/M5475GFE.dts b/arch/m68k/dts/M5475GFE.dts deleted file mode 100644 index 75080fa737..0000000000 --- a/arch/m68k/dts/M5475GFE.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it> - */ - -/dts-v1/; -/include/ "mcf54xx.dtsi" - -/ { - model = "Freescale M5475GFE"; - compatible = "fsl,M5475GFE"; -}; - -&fec0 { - status = "okay"; -}; - -&fec1 { - status = "okay"; - mii-base = <0>; -}; diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile index 0a356b8e37..47260a101d 100644 --- a/arch/m68k/dts/Makefile +++ b/arch/m68k/dts/Makefile @@ -32,13 +32,6 @@ dtb-$(CONFIG_TARGET_M54455EVB) += M54455EVB.dtb \ M54455EVB_i66.dtb dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb -dtb-$(CONFIG_TARGET_M5475EVB) += M5475AFE.dtb \ - M5475BFE.dtb \ - M5475CFE.dtb \ - M5475DFE.dtb \ - M5475EFE.dtb \ - M5475FFE.dtb \ - M5475GFE.dtb targets += $(dtb-y) diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index a1eeabc2af..fabec0ae92 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -19,7 +19,7 @@ #define CONFIG_CF_V3 #endif -#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x) +#if defined(CONFIG_MCF5445x) #define CONFIG_CF_V4 #elif defined(CONFIG_MCF5441x) #define CONFIG_CF_V4E /* Four Extra ACRn */ diff --git a/arch/m68k/include/asm/coldfire/dspi.h b/arch/m68k/include/asm/coldfire/dspi.h index ddd8f33805..7848dbdff4 100644 --- a/arch/m68k/include/asm/coldfire/dspi.h +++ b/arch/m68k/include/asm/coldfire/dspi.h @@ -20,14 +20,8 @@ typedef struct dspi { u32 tfr; /* 0x34 - PUSHR */ u16 resv1; /* 0x38 */ u16 rfr; /* 0x3A - POPR */ -#ifdef CONFIG_MCF547x_8x - u32 tfdr[4]; /* 0x3C */ - u8 resv2[0x30]; /* 0x40 */ - u32 rfdr[4]; /* 0x7C */ -#else u32 tfdr[16]; /* 0x3C */ u32 rfdr[16]; /* 0x7C */ -#endif } dspi_t; /* Module configuration */ diff --git a/arch/m68k/include/asm/coldfire/eport.h b/arch/m68k/include/asm/coldfire/eport.h index 0e64bef5ed..eb5c666361 100644 --- a/arch/m68k/include/asm/coldfire/eport.h +++ b/arch/m68k/include/asm/coldfire/eport.h @@ -11,18 +11,6 @@ /* Edge Port Module (EPORT) */ typedef struct eport { -#ifdef CONFIG_MCF547x_8x - u16 par; /* 0x00 */ - u16 res0; /* 0x02 */ - u8 ddr; /* 0x04 */ - u8 ier; /* 0x05 */ - u16 res1; /* 0x06 */ - u8 dr; /* 0x08 */ - u8 pdr; /* 0x09 */ - u16 res2; /* 0x0A */ - u8 fr; /* 0x0C */ - u8 res3[3]; /* 0x0D */ -#else u16 par; /* 0x00 Pin Assignment */ u8 ddr; /* 0x02 Data Direction */ u8 ier; /* 0x03 Interrupt Enable */ @@ -30,7 +18,6 @@ typedef struct eport { u8 pdr; /* 0x05 Pin Data */ u8 fr; /* 0x06 Flag */ u8 res0; -#endif } eport_t; /* EPPAR */ diff --git a/arch/m68k/include/asm/fec.h b/arch/m68k/include/asm/fec.h index cdb8119d3e..759c8cfc43 100644 --- a/arch/m68k/include/asm/fec.h +++ b/arch/m68k/include/asm/fec.h @@ -337,13 +337,8 @@ typedef struct fec { #define FEC_RESET_DELAY 100 #define FEC_RX_TOUT 100 -#ifdef CONFIG_MCF547x_8x -typedef struct fec_info_dma fec_info_t; -#define FEC_T fecdma_t -#else typedef struct fec_info_s fec_info_t; #define FEC_T fec_t -#endif int fecpin_setclear(fec_info_t *info, int setclear); int mii_discover_phy(fec_info_t *info); diff --git a/arch/m68k/include/asm/immap_547x_8x.h b/arch/m68k/include/asm/immap_547x_8x.h deleted file mode 100644 index 5e1345684d..0000000000 --- a/arch/m68k/include/asm/immap_547x_8x.h +++ /dev/null @@ -1,258 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * MCF547x_8x Internal Memory Map - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#ifndef __IMMAP_547x_8x__ -#define __IMMAP_547x_8x__ - -#define MMAP_SIU (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_XARB (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000500) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000700) -#define MMAP_GPTMR (CONFIG_SYS_MBAR + 0x00000800) -#define MMAP_SLT0 (CONFIG_SYS_MBAR + 0x00000900) -#define MMAP_SLT1 (CONFIG_SYS_MBAR + 0x00000910) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000A00) -#define MMAP_PCI (CONFIG_SYS_MBAR + 0x00000B00) -#define MMAP_PCIARB (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_EXTDMA (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_CTM (CONFIG_SYS_MBAR + 0x00007F00) -#define MMAP_MCDMA (CONFIG_SYS_MBAR + 0x00008000) -#define MMAP_SCPCI (CONFIG_SYS_MBAR + 0x00008400) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00008600) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00008700) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00008800) -#define MMAP_UART3 (CONFIG_SYS_MBAR + 0x00008900) -#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x00008A00) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00008F00) -#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00009000) -#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00009800) -#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x0000A000) -#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x0000A800) -#define MMAP_USBD (CONFIG_SYS_MBAR + 0x0000B000) -#define MMAP_SRAM (CONFIG_SYS_MBAR + 0x00010000) -#define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001FF00) -#define MMAP_SEC (CONFIG_SYS_MBAR + 0x00020000) - -#include <asm/coldfire/dspi.h> -#include <asm/coldfire/eport.h> -#include <asm/coldfire/flexbus.h> -#include <asm/coldfire/flexcan.h> -#include <asm/coldfire/intctrl.h> - -typedef struct siu { - u32 mbar; /* 0x00 */ - u32 drv; /* 0x04 */ - u32 rsvd1[2]; /* 0x08 - 0x1F */ - u32 sbcr; /* 0x10 */ - u32 rsvd2[3]; /* 0x14 - 0x1F */ - u32 cs0cfg; /* 0x20 */ - u32 cs1cfg; /* 0x24 */ - u32 cs2cfg; /* 0x28 */ - u32 cs3cfg; /* 0x2C */ - u32 rsvd3[2]; /* 0x30 - 0x37 */ - u32 secsacr; /* 0x38 */ - u32 rsvd4[2]; /* 0x3C - 0x43 */ - u32 rsr; /* 0x44 */ - u32 rsvd5[2]; /* 0x48 - 0x4F */ - u32 jtagid; /* 0x50 */ -} siu_t; - -typedef struct sdram { - u32 mode; /* 0x00 */ - u32 ctrl; /* 0x04 */ - u32 cfg1; /* 0x08 */ - u32 cfg2; /* 0x0c */ -} sdram_t; - -typedef struct xlb_arb { - u32 cfg; /* 0x240 */ - u32 ver; /* 0x244 */ - u32 sr; /* 0x248 */ - u32 imr; /* 0x24c */ - u32 adrcap; /* 0x250 */ - u32 sigcap; /* 0x254 */ - u32 adrto; /* 0x258 */ - u32 datto; /* 0x25c */ - u32 busto; /* 0x260 */ - u32 prien; /* 0x264 */ - u32 pri; /* 0x268 */ -} xlbarb_t; - -typedef struct gptmr { - u8 ocpw; - u8 octict; - u8 ctrl; - u8 mode; - - u16 pre; /* Prescale */ - u16 cnt; - - u16 pwmwidth; - u8 pwmop; /* Output Polarity */ - u8 pwmld; /* Immediate Update */ - - u16 cap; /* Capture internal counter */ - u8 ovfpin; /* Ovf and Pin */ - u8 intr; /* Interrupts */ -} gptmr_t; - -typedef struct canex_ctrl { - can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */ -} canex_t; - - -typedef struct slt { - u32 tcnt; /* 0x00 */ - u32 cr; /* 0x04 */ - u32 cnt; /* 0x08 */ - u32 sr; /* 0x0C */ -} slt_t; - -typedef struct gpio { - /* Port Output Data Registers */ - u8 podr_fbctl; /*0x00 */ - u8 podr_fbcs; /*0x01 */ - u8 podr_dma; /*0x02 */ - u8 rsvd1; /*0x03 */ - u8 podr_fec0h; /*0x04 */ - u8 podr_fec0l; /*0x05 */ - u8 podr_fec1h; /*0x06 */ - u8 podr_fec1l; /*0x07 */ - u8 podr_feci2c; /*0x08 */ - u8 podr_pcibg; /*0x09 */ - u8 podr_pcibr; /*0x0A */ - u8 rsvd2; /*0x0B */ - u8 podr_psc3psc2; /*0x0C */ - u8 podr_psc1psc0; /*0x0D */ - u8 podr_dspi; /*0x0E */ - u8 rsvd3; /*0x0F */ - - /* Port Data Direction Registers */ - u8 pddr_fbctl; /*0x10 */ - u8 pddr_fbcs; /*0x11 */ - u8 pddr_dma; /*0x12 */ - u8 rsvd4; /*0x13 */ - u8 pddr_fec0h; /*0x14 */ - u8 pddr_fec0l; /*0x15 */ - u8 pddr_fec1h; /*0x16 */ - u8 pddr_fec1l; /*0x17 */ - u8 pddr_feci2c; /*0x18 */ - u8 pddr_pcibg; /*0x19 */ - u8 pddr_pcibr; /*0x1A */ - u8 rsvd5; /*0x1B */ - u8 pddr_psc3psc2; /*0x1C */ - u8 pddr_psc1psc0; /*0x1D */ - u8 pddr_dspi; /*0x1E */ - u8 rsvd6; /*0x1F */ - - /* Port Pin Data/Set Data Registers */ - u8 ppdsdr_fbctl; /*0x20 */ - u8 ppdsdr_fbcs; /*0x21 */ - u8 ppdsdr_dma; /*0x22 */ - u8 rsvd7; /*0x23 */ - u8 ppdsdr_fec0h; /*0x24 */ - u8 ppdsdr_fec0l; /*0x25 */ - u8 ppdsdr_fec1h; /*0x26 */ - u8 ppdsdr_fec1l; /*0x27 */ - u8 ppdsdr_feci2c; /*0x28 */ - u8 ppdsdr_pcibg; /*0x29 */ - u8 ppdsdr_pcibr; /*0x2A */ - u8 rsvd8; /*0x2B */ - u8 ppdsdr_psc3psc2; /*0x2C */ - u8 ppdsdr_psc1psc0; /*0x2D */ - u8 ppdsdr_dspi; /*0x2E */ - u8 rsvd9; /*0x2F */ - - /* Port Clear Output Data Registers */ - u8 pclrr_fbctl; /*0x30 */ - u8 pclrr_fbcs; /*0x31 */ - u8 pclrr_dma; /*0x32 */ - u8 rsvd10; /*0x33 */ - u8 pclrr_fec0h; /*0x34 */ - u8 pclrr_fec0l; /*0x35 */ - u8 pclrr_fec1h; /*0x36 */ - u8 pclrr_fec1l; /*0x37 */ - u8 pclrr_feci2c; /*0x38 */ - u8 pclrr_pcibg; /*0x39 */ - u8 pclrr_pcibr; /*0x3A */ - u8 rsvd11; /*0x3B */ - u8 pclrr_psc3psc2; /*0x3C */ - u8 pclrr_psc1psc0; /*0x3D */ - u8 pclrr_dspi; /*0x3E */ - u8 rsvd12; /*0x3F */ - - /* Pin Assignment Registers */ - u16 par_fbctl; /*0x40 */ - u8 par_fbcs; /*0x42 */ - u8 par_dma; /*0x43 */ - u16 par_feci2cirq; /*0x44 */ - u16 rsvd13; /*0x46 */ - u16 par_pcibg; /*0x48 */ - u16 par_pcibr; /*0x4A */ - u8 par_psc3; /*0x4C */ - u8 par_psc2; /*0x4D */ - u8 par_psc1; /*0x4E */ - u8 par_psc0; /*0x4F */ - u16 par_dspi; /*0x50 */ - u8 par_timer; /*0x52 */ - u8 rsvd14; /*0x53 */ -} gpio_t; - -typedef struct pci { - u32 idr; /* 0x00 Device Id / Vendor Id */ - u32 scr; /* 0x04 Status / command */ - u32 ccrir; /* 0x08 Class Code / Revision Id */ - u32 cr1; /* 0x0c Configuration 1 */ - u32 bar0; /* 0x10 Base address register 0 */ - u32 bar1; /* 0x14 Base address register 1 */ - u32 bar2; /* 0x18 NA */ - u32 bar3; /* 0x1c NA */ - u32 bar4; /* 0x20 NA */ - u32 bar5; /* 0x24 NA */ - u32 ccpr; /* 0x28 Cardbus CIS Pointer */ - u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID */ - u32 erbar; /* 0x30 Expansion ROM Base Address */ - u32 cpr; /* 0x34 Capabilities Pointer */ - u32 rsvd1; /* 0x38 */ - u32 cr2; /* 0x3c Configuration 2 */ - u32 rsvd2[8]; /* 0x40 - 0x5f */ - - /* General control / status registers */ - u32 gscr; /* 0x60 Global Status / Control */ - u32 tbatr0a; /* 0x64 Target Base Adr Translation 0 */ - u32 tbatr1a; /* 0x68 Target Base Adr Translation 1 */ - u32 tcr1; /* 0x6c Target Control 1 Register */ - u32 iw0btar; /* 0x70 Initiator Win 0 Base/Translation adr */ - u32 iw1btar; /* 0x74 Initiator Win 1 Base/Translation adr */ - u32 iw2btar; /* 0x78 NA */ - u32 rsvd3; /* 0x7c */ - u32 iwcr; /* 0x80 Initiator Window Configuration */ - u32 icr; /* 0x84 Initiator Control */ - u32 isr; /* 0x88 Initiator Status */ - u32 tcr2; /* 0x8c NA */ - u32 tbatr0; /* 0x90 NA */ - u32 tbatr1; /* 0x94 NA */ - u32 tbatr2; /* 0x98 NA */ - u32 tbatr3; /* 0x9c NA */ - u32 tbatr4; /* 0xa0 NA */ - u32 tbatr5; /* 0xa4 NA */ - u32 intr; /* 0xa8 NA */ - u32 rsvd4[19]; /* 0xac - 0xf7 */ - u32 car; /* 0xf8 Configuration Address */ -} pci_t; - -typedef struct pci_arbiter { - /* Pci Arbiter Registers */ - union { - u32 acr; /* Arbiter Control */ - u32 asr; /* Arbiter Status */ - }; -} pciarb_t; -#endif /* __IMMAP_547x_8x__ */ diff --git a/arch/m68k/include/asm/m547x_8x.h b/arch/m68k/include/asm/m547x_8x.h deleted file mode 100644 index 30f12004b7..0000000000 --- a/arch/m68k/include/asm/m547x_8x.h +++ /dev/null @@ -1,417 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * mcf547x_8x.h -- Definitions for Freescale Coldfire 547x_8x - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#ifndef mcf547x_8x_h -#define mcf547x_8x_h - -/********************************************************************* -* XLB Arbiter (XLB) -*********************************************************************/ -/* Bit definitions and macros for XARB_CFG */ -#define XARB_CFG_AT (0x00000002) -#define XARB_CFG_DT (0x00000004) -#define XARB_CFG_BA (0x00000008) -#define XARB_CFG_PM(x) (((x)&0x00000003)<<5) -#define XARB_CFG_SP(x) (((x)&0x00000007)<<8) -#define XARB_CFG_PLDIS (0x80000000) - -/* Bit definitions and macros for XARB_SR */ -#define XARB_SR_AT (0x00000001) -#define XARB_SR_DT (0x00000002) -#define XARB_SR_BA (0x00000004) -#define XARB_SR_TTM (0x00000008) -#define XARB_SR_ECW (0x00000010) -#define XARB_SR_TTR (0x00000020) -#define XARB_SR_TTA (0x00000040) -#define XARB_SR_MM (0x00000080) -#define XARB_SR_SEA (0x00000100) - -/* Bit definitions and macros for XARB_IMR */ -#define XARB_IMR_ATE (0x00000001) -#define XARB_IMR_DTE (0x00000002) -#define XARB_IMR_BAE (0x00000004) -#define XARB_IMR_TTME (0x00000008) -#define XARB_IMR_ECWE (0x00000010) -#define XARB_IMR_TTRE (0x00000020) -#define XARB_IMR_TTAE (0x00000040) -#define XARB_IMR_MME (0x00000080) -#define XARB_IMR_SEAE (0x00000100) - -/* Bit definitions and macros for XARB_SIGCAP */ -#define XARB_SIGCAP_TT(x) ((x)&0x0000001F) -#define XARB_SIGCAP_TBST (0x00000020) -#define XARB_SIGCAP_TSIZ(x) (((x)&0x00000007)<<7) - -/* Bit definitions and macros for XARB_PRIEN */ -#define XARB_PRIEN_M0 (0x00000001) -#define XARB_PRIEN_M2 (0x00000004) -#define XARB_PRIEN_M3 (0x00000008) - -/* Bit definitions and macros for XARB_PRI */ -#define XARB_PRI_M0P(x) (((x)&0x00000007)<<0) -#define XARB_PRI_M2P(x) (((x)&0x00000007)<<8) -#define XARB_PRI_M3P(x) (((x)&0x00000007)<<12) - -/********************************************************************* -* General Purpose I/O (GPIO) -*********************************************************************/ -/* Bit definitions and macros for GPIO_PAR_FBCTL */ -#define GPIO_PAR_FBCTL_TS(x) (((x)&0x0003)<<0) -#define GPIO_PAR_FBCTL_TA (0x0004) -#define GPIO_PAR_FBCTL_RWB(x) (((x)&0x0003)<<4) -#define GPIO_PAR_FBCTL_OE (0x0040) -#define GPIO_PAR_FBCTL_BWE0 (0x0100) -#define GPIO_PAR_FBCTL_BWE1 (0x0400) -#define GPIO_PAR_FBCTL_BWE2 (0x1000) -#define GPIO_PAR_FBCTL_BWE3 (0x4000) -#define GPIO_PAR_FBCTL_TS_GPIO (0) -#define GPIO_PAR_FBCTL_TS_TBST (2) -#define GPIO_PAR_FBCTL_TS_TS (3) -#define GPIO_PAR_FBCTL_RWB_GPIO (0x0000) -#define GPIO_PAR_FBCTL_RWB_TBST (0x0020) -#define GPIO_PAR_FBCTL_RWB_RWB (0x0030) - -/* Bit definitions and macros for GPIO_PAR_FBCS */ -#define GPIO_PAR_FBCS_CS1 (0x02) -#define GPIO_PAR_FBCS_CS2 (0x04) -#define GPIO_PAR_FBCS_CS3 (0x08) -#define GPIO_PAR_FBCS_CS4 (0x10) -#define GPIO_PAR_FBCS_CS5 (0x20) - -/* Bit definitions and macros for GPIO_PAR_DMA */ -#define GPIO_PAR_DMA_DREQ0(x) (((x)&0x03)<<0) -#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<2) -#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<4) -#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6) -#define GPIO_PAR_DMA_DACKx_GPIO (0) -#define GPIO_PAR_DMA_DACKx_TOUT (2) -#define GPIO_PAR_DMA_DACKx_DACK (3) -#define GPIO_PAR_DMA_DREQx_GPIO (0) -#define GPIO_PAR_DMA_DREQx_TIN (2) -#define GPIO_PAR_DMA_DREQx_DREQ (3) - -/* Bit definitions and macros for GPIO_PAR_FECI2CIRQ */ -#define GPIO_PAR_FECI2CIRQ_IRQ5 (0x0001) -#define GPIO_PAR_FECI2CIRQ_IRQ6 (0x0002) -#define GPIO_PAR_FECI2CIRQ_SCL (0x0004) -#define GPIO_PAR_FECI2CIRQ_SDA (0x0008) -#define GPIO_PAR_FECI2CIRQ_E1MDC(x) (((x)&0x0003)<<6) -#define GPIO_PAR_FECI2CIRQ_E1MDIO(x) (((x)&0x0003)<<8) -#define GPIO_PAR_FECI2CIRQ_E1MII (0x0400) -#define GPIO_PAR_FECI2CIRQ_E17 (0x0800) -#define GPIO_PAR_FECI2CIRQ_E0MDC (0x1000) -#define GPIO_PAR_FECI2CIRQ_E0MDIO (0x2000) -#define GPIO_PAR_FECI2CIRQ_E0MII (0x4000) -#define GPIO_PAR_FECI2CIRQ_E07 (0x8000) -#define GPIO_PAR_FECI2CIRQ_E1MDIO_CANRX (0x0000) -#define GPIO_PAR_FECI2CIRQ_E1MDIO_SDA (0x0200) -#define GPIO_PAR_FECI2CIRQ_E1MDIO_EMDIO (0x0300) -#define GPIO_PAR_FECI2CIRQ_E1MDC_CANTX (0x0000) -#define GPIO_PAR_FECI2CIRQ_E1MDC_SCL (0x0080) -#define GPIO_PAR_FECI2CIRQ_E1MDC_EMDC (0x00C0) - -/* Bit definitions and macros for GPIO_PAR_PCIBG */ -#define GPIO_PAR_PCIBG_PCIBG0(x) (((x)&0x0003)<<0) -#define GPIO_PAR_PCIBG_PCIBG1(x) (((x)&0x0003)<<2) -#define GPIO_PAR_PCIBG_PCIBG2(x) (((x)&0x0003)<<4) -#define GPIO_PAR_PCIBG_PCIBG3(x) (((x)&0x0003)<<6) -#define GPIO_PAR_PCIBG_PCIBG4(x) (((x)&0x0003)<<8) - -/* Bit definitions and macros for GPIO_PAR_PCIBR */ -#define GPIO_PAR_PCIBR_PCIBR0(x) (((x)&0x0003)<<0) -#define GPIO_PAR_PCIBR_PCIBR1(x) (((x)&0x0003)<<2) -#define GPIO_PAR_PCIBR_PCIBR2(x) (((x)&0x0003)<<4) -#define GPIO_PAR_PCIBR_PCIBR3(x) (((x)&0x0003)<<6) -#define GPIO_PAR_PCIBR_PCIBR4(x) (((x)&0x0003)<<8) - -/* Bit definitions and macros for GPIO_PAR_PSC3 */ -#define GPIO_PAR_PSC3_TXD3 (0x04) -#define GPIO_PAR_PSC3_RXD3 (0x08) -#define GPIO_PAR_PSC3_RTS3(x) (((x)&0x03)<<4) -#define GPIO_PAR_PSC3_CTS3(x) (((x)&0x03)<<6) -#define GPIO_PAR_PSC3_CTS3_GPIO (0x00) -#define GPIO_PAR_PSC3_CTS3_BCLK (0x80) -#define GPIO_PAR_PSC3_CTS3_CTS (0xC0) -#define GPIO_PAR_PSC3_RTS3_GPIO (0x00) -#define GPIO_PAR_PSC3_RTS3_FSYNC (0x20) -#define GPIO_PAR_PSC3_RTS3_RTS (0x30) -#define GPIO_PAR_PSC3_CTS2_CANRX (0x40) - -/* Bit definitions and macros for GPIO_PAR_PSC2 */ -#define GPIO_PAR_PSC2_TXD2 (0x04) -#define GPIO_PAR_PSC2_RXD2 (0x08) -#define GPIO_PAR_PSC2_RTS2(x) (((x)&0x03)<<4) -#define GPIO_PAR_PSC2_CTS2(x) (((x)&0x03)<<6) -#define GPIO_PAR_PSC2_CTS2_GPIO (0x00) -#define GPIO_PAR_PSC2_CTS2_BCLK (0x80) -#define GPIO_PAR_PSC2_CTS2_CTS (0xC0) -#define GPIO_PAR_PSC2_RTS2_GPIO (0x00) -#define GPIO_PAR_PSC2_RTS2_CANTX (0x10) -#define GPIO_PAR_PSC2_RTS2_FSYNC (0x20) -#define GPIO_PAR_PSC2_RTS2_RTS (0x30) - -/* Bit definitions and macros for GPIO_PAR_PSC1 */ -#define GPIO_PAR_PSC1_TXD1 (0x04) -#define GPIO_PAR_PSC1_RXD1 (0x08) -#define GPIO_PAR_PSC1_RTS1(x) (((x)&0x03)<<4) -#define GPIO_PAR_PSC1_CTS1(x) (((x)&0x03)<<6) -#define GPIO_PAR_PSC1_CTS1_GPIO (0x00) -#define GPIO_PAR_PSC1_CTS1_BCLK (0x80) -#define GPIO_PAR_PSC1_CTS1_CTS (0xC0) -#define GPIO_PAR_PSC1_RTS1_GPIO (0x00) -#define GPIO_PAR_PSC1_RTS1_FSYNC (0x20) -#define GPIO_PAR_PSC1_RTS1_RTS (0x30) - -/* Bit definitions and macros for GPIO_PAR_PSC0 */ -#define GPIO_PAR_PSC0_TXD0 (0x04) -#define GPIO_PAR_PSC0_RXD0 (0x08) -#define GPIO_PAR_PSC0_RTS0(x) (((x)&0x03)<<4) -#define GPIO_PAR_PSC0_CTS0(x) (((x)&0x03)<<6) -#define GPIO_PAR_PSC0_CTS0_GPIO (0x00) -#define GPIO_PAR_PSC0_CTS0_BCLK (0x80) -#define GPIO_PAR_PSC0_CTS0_CTS (0xC0) -#define GPIO_PAR_PSC0_RTS0_GPIO (0x00) -#define GPIO_PAR_PSC0_RTS0_FSYNC (0x20) -#define GPIO_PAR_PSC0_RTS0_RTS (0x30) - -/* Bit definitions and macros for GPIO_PAR_DSPI */ -#define GPIO_PAR_DSPI_SOUT(x) (((x)&0x0003)<<0) -#define GPIO_PAR_DSPI_SIN(x) (((x)&0x0003)<<2) -#define GPIO_PAR_DSPI_SCK(x) (((x)&0x0003)<<4) -#define GPIO_PAR_DSPI_CS0(x) (((x)&0x0003)<<6) -#define GPIO_PAR_DSPI_CS2(x) (((x)&0x0003)<<8) -#define GPIO_PAR_DSPI_CS3(x) (((x)&0x0003)<<10) -#define GPIO_PAR_DSPI_CS5 (0x1000) -#define GPIO_PAR_DSPI_CS3_GPIO (0x0000) -#define GPIO_PAR_DSPI_CS3_CANTX (0x0400) -#define GPIO_PAR_DSPI_CS3_TOUT (0x0800) -#define GPIO_PAR_DSPI_CS3_DSPICS (0x0C00) -#define GPIO_PAR_DSPI_CS2_GPIO (0x0000) -#define GPIO_PAR_DSPI_CS2_CANTX (0x0100) -#define GPIO_PAR_DSPI_CS2_TOUT (0x0200) -#define GPIO_PAR_DSPI_CS2_DSPICS (0x0300) -#define GPIO_PAR_DSPI_CS0_GPIO (0x0000) -#define GPIO_PAR_DSPI_CS0_FSYNC (0x0040) -#define GPIO_PAR_DSPI_CS0_RTS (0x0080) -#define GPIO_PAR_DSPI_CS0_DSPICS (0x00C0) -#define GPIO_PAR_DSPI_SCK_GPIO (0x0000) -#define GPIO_PAR_DSPI_SCK_BCLK (0x0010) -#define GPIO_PAR_DSPI_SCK_CTS (0x0020) -#define GPIO_PAR_DSPI_SCK_SCK (0x0030) -#define GPIO_PAR_DSPI_SIN_GPIO (0x0000) -#define GPIO_PAR_DSPI_SIN_RXD (0x0008) -#define GPIO_PAR_DSPI_SIN_SIN (0x000C) -#define GPIO_PAR_DSPI_SOUT_GPIO (0x0000) -#define GPIO_PAR_DSPI_SOUT_TXD (0x0002) -#define GPIO_PAR_DSPI_SOUT_SOUT (0x0003) - -/* Bit definitions and macros for GPIO_PAR_TIMER */ -#define GPIO_PAR_TIMER_TOUT2 (0x01) -#define GPIO_PAR_TIMER_TIN2(x) (((x)&0x03)<<1) -#define GPIO_PAR_TIMER_TOUT3 (0x08) -#define GPIO_PAR_TIMER_TIN3(x) (((x)&0x03)<<4) -#define GPIO_PAR_TIMER_TIN3_CANRX (0x00) -#define GPIO_PAR_TIMER_TIN3_IRQ (0x20) -#define GPIO_PAR_TIMER_TIN3_TIN (0x30) -#define GPIO_PAR_TIMER_TIN2_CANRX (0x00) -#define GPIO_PAR_TIMER_TIN2_IRQ (0x04) -#define GPIO_PAR_TIMER_TIN2_TIN (0x06) - -/********************************************************************* -* Slice Timer (SLT) -*********************************************************************/ -#define SLT_CR_RUN (0x04000000) -#define SLT_CR_IEN (0x02000000) -#define SLT_CR_TEN (0x01000000) - -#define SLT_SR_BE (0x02000000) -#define SLT_SR_ST (0x01000000) - -/********************************************************************* -* Interrupt Controller (INTC) -*********************************************************************/ -#define INT0_LO_RSVD0 (0) -#define INT0_LO_EPORT1 (1) -#define INT0_LO_EPORT2 (2) -#define INT0_LO_EPORT3 (3) -#define INT0_LO_EPORT4 (4) -#define INT0_LO_EPORT5 (5) -#define INT0_LO_EPORT6 (6) -#define INT0_LO_EPORT7 (7) -#define INT0_LO_EP0ISR (15) -#define INT0_LO_EP1ISR (16) -#define INT0_LO_EP2ISR (17) -#define INT0_LO_EP3ISR (18) -#define INT0_LO_EP4ISR (19) -#define INT0_LO_EP5ISR (20) -#define INT0_LO_EP6ISR (21) -#define INT0_LO_USBISR (22) -#define INT0_LO_USBAISR (23) -#define INT0_LO_USB (24) -#define INT1_LO_DSPI_RFOF_TFUF (25) -#define INT1_LO_DSPI_RFOF (26) -#define INT1_LO_DSPI_RFDF (27) -#define INT1_LO_DSPI_TFUF (28) -#define INT1_LO_DSPI_TCF (29) -#define INT1_LO_DSPI_TFFF (30) -#define INT1_LO_DSPI_EOQF (31) - -#define INT0_HI_UART3 (32) -#define INT0_HI_UART2 (33) -#define INT0_HI_UART1 (34) -#define INT0_HI_UART0 (35) -#define INT0_HI_COMMTIM_TC (36) -#define INT0_HI_SEC (37) -#define INT0_HI_FEC1 (38) -#define INT0_HI_FEC0 (39) -#define INT0_HI_I2C (40) -#define INT0_HI_PCIARB (41) -#define INT0_HI_CBPCI (42) -#define INT0_HI_XLBPCI (43) -#define INT0_HI_XLBARB (47) -#define INT0_HI_DMA (48) -#define INT0_HI_CAN0_ERROR (49) -#define INT0_HI_CAN0_BUSOFF (50) -#define INT0_HI_CAN0_MBOR (51) -#define INT0_HI_SLT1 (53) -#define INT0_HI_SLT0 (54) -#define INT0_HI_CAN1_ERROR (55) -#define INT0_HI_CAN1_BUSOFF (56) -#define INT0_HI_CAN1_MBOR (57) -#define INT0_HI_GPT3 (59) -#define INT0_HI_GPT2 (60) -#define INT0_HI_GPT1 (61) -#define INT0_HI_GPT0 (62) - -/********************************************************************* -* General Purpose Timers (GPTMR) -*********************************************************************/ -/* Enable and Mode Select */ -#define GPT_OCT(x) (x & 0x3)<<4 /* Output Compare Type */ -#define GPT_ICT(x) (x & 0x3) /* Input Capture Type */ -#define GPT_CTRL_WDEN 0x80 /* Watchdog Enable */ -#define GPT_CTRL_CE 0x10 /* Counter Enable */ -#define GPT_CTRL_STPCNT 0x04 /* Stop continous */ -#define GPT_CTRL_ODRAIN 0x02 /* Open Drain */ -#define GPT_CTRL_INTEN 0x01 /* Interrupt Enable */ -#define GPT_MODE_GPIO(x) (x & 0x3)<<4 /* Gpio Mode Type */ -#define GPT_TMS_ICT 0x01 /* Input Capture Enable */ -#define GPT_TMS_OCT 0x02 /* Output Capture Enable */ -#define GPT_TMS_PWM 0x03 /* PWM Capture Enable */ -#define GPT_TMS_SGPIO 0x04 /* PWM Capture Enable */ - -#define GPT_PWM_WIDTH(x) (x & 0xffff) - -/* Status */ -#define GPT_STA_CAPTURE(x) (x & 0xffff) - -#define GPT_OVFPIN_OVF(x) (x & 0x70) -#define GPT_OVFPIN_PIN 0x01 - -#define GPT_INT_TEXP 0x08 -#define GPT_INT_PWMP 0x04 -#define GPT_INT_COMP 0x02 -#define GPT_INT_CAPT 0x01 - -/********************************************************************* -* PCI -*********************************************************************/ - -/* Bit definitions and macros for SCR */ -#define PCI_SCR_PE (0x80000000) /* Parity Error detected */ -#define PCI_SCR_SE (0x40000000) /* System error signalled */ -#define PCI_SCR_MA (0x20000000) /* Master aboart received */ -#define PCI_SCR_TR (0x10000000) /* Target abort received */ -#define PCI_SCR_TS (0x08000000) /* Target abort signalled */ -#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */ -#define PCI_SCR_DP (0x01000000) /* Master data parity err */ -#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */ -#define PCI_SCR_R (0x00400000) /* Reserved */ -#define PCI_SCR_66M (0x00200000) /* 66Mhz */ -#define PCI_SCR_C (0x00100000) /* Capabilities list */ -#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */ -#define PCI_SCR_S (0x00000100) /* SERR enable */ -#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */ -#define PCI_SCR_PER (0x00000040) /* Parity error response */ -#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */ -#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */ -#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */ -#define PCI_SCR_B (0x00000004) /* Bus master enable */ -#define PCI_SCR_M (0x00000002) /* Memory access control */ -#define PCI_SCR_IO (0x00000001) /* I/O access control */ - -#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */ -#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */ -#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */ -#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */ - -#define PCI_BAR_BAR0(x) (x & 0xFFFC0000) -#define PCI_BAR_BAR1(x) (x & 0xC0000000) -#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */ -#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */ -#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */ - -#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */ -#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */ -#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */ -#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */ - -#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */ -#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */ -#define PCI_GSCR_SE (0x10000000) /* SERR detected */ -#define PCI_GSCR_ER (0x08000000) /* Error response detected */ -#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */ -#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */ -#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */ -#define PCI_GSCR_PR (0x00000001) /* PCI reset */ - -#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */ -#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */ -#define PCI_TCR1_P (0x00010000) /* Prefetch reads */ -#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */ - -#define PCI_TCR1_B5E (0x00002000) /* */ -#define PCI_TCR1_B4E (0x00001000) /* */ -#define PCI_TCR1_B3E (0x00000800) /* */ -#define PCI_TCR1_B2E (0x00000400) /* */ -#define PCI_TCR1_B1E (0x00000200) /* */ -#define PCI_TCR1_B0E (0x00000100) /* */ -#define PCI_TCR1_CR (0x00000001) /* */ - -#define PCI_TBATR_BAT0(x) (x & 0xFFFC0000) -#define PCI_TBATR_BAT1(x) (x & 0xC0000000) -#define PCI_TBATR_EN (0x00000001) /* Enable */ - -#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */ -#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */ -#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */ -#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */ -#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */ -#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */ -#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */ -#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */ -#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */ -#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */ -#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */ -#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */ -#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */ -#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */ -#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */ - -#define PCI_ICR_REE (0x04000000) /* Retry error enable */ -#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */ -#define PCI_ICR_TAE (0x01000000) /* Target abort enable */ -#define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF) - -#define PCIARB_ACR_DS (0x80000000) -#define PCIARB_ARC_EXTMINTEN(x) (((x)&0x1F) << 17) -#define PCIARB_ARC_INTMINTEN (0x00010000) -#define PCIARB_ARC_EXTMPRI(x) (((x)&0x1F) << 1) -#define PCIARB_ARC_INTMPRI (0x00000001) - -#endif /* mcf547x_8x_h */ diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c index 68f2eef584..aa2b93e0e0 100644 --- a/arch/m68k/lib/cache.c +++ b/arch/m68k/lib/cache.c @@ -80,7 +80,7 @@ void icache_invalid(void) } /* - * data cache only for ColdFire V4 such as MCF547x_8x, MCF5445x + * data cache only for ColdFire V4 such as MCF5445x * the dcache will be dummy in ColdFire V2 and V3 */ void dcache_enable(void) |