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| author | Tom Rini <trini@konsulko.com> | 2020-04-21 15:20:42 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-04-21 15:20:42 -0400 |
| commit | bdcb29960e3a9558803632783b922f26993d219e (patch) | |
| tree | c0c343ca723b8736b74af172bb47f1007dc2fc5c /arch/arm | |
| parent | 1bf65142b31a48c8e354df603c9f6fa5c8cac389 (diff) | |
| parent | e174fb7061e7a3f1996f57eb36525c51dd87b5a3 (diff) | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Backplane support and bug fixes
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 9 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 5 |
2 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 87c3e05f45..077438765c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2015 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include <common.h> @@ -31,6 +32,14 @@ int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { + const char *conn; + + /* Do NOT apply fixup for backplane modes specified in DT */ + if (phyc == PHY_INTERFACE_MODE_XGMII) { + conn = fdt_getprop(blob, offset, "phy-connection-type", NULL); + if (is_backplane_mode(conn)) + return 0; + } return fdt_setprop_string(blob, offset, "phy-connection-type", phy_string_for_interface(phyc)); } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 299201b157..c2fbc23b11 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -232,7 +232,12 @@ #define DCFG_PORSR1 0x000 #define DCFG_PORSR1_RCW_SRC 0xff800000 #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 +#define DCFG_RCWSR12 0x12c +#define DCFG_RCWSR12_SDHC_SHIFT 24 +#define DCFG_RCWSR12_SDHC_MASK 0x7 #define DCFG_RCWSR13 0x130 +#define DCFG_RCWSR13_SDHC_SHIFT 3 +#define DCFG_RCWSR13_SDHC_MASK 0x7 #define DCFG_RCWSR13_DSPI (0 << 8) #define DCFG_RCWSR15 0x138 #define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3 |