diff options
author | Ye Li <ye.li@nxp.com> | 2019-07-22 01:25:10 +0000 |
---|---|---|
committer | Stefano Babic <sbabic@denx.de> | 2019-10-08 16:35:16 +0200 |
commit | 971a71e114d00ceee7b486d4599d3c26756109fb (patch) | |
tree | dce83e5db4aab27577cb22e1261670aba2c6bc54 /arch/arm | |
parent | df3572e93033d7620767ed6dc9790dceb110636c (diff) |
i.MX7ULP: Change clock rate calculation for NIC1 BUS and EXT
On i.MX7ULP B0, there is change in NIC clock dividers architecture.
On A0, the NIC1 BUS and EXT dividers were in a chain with NIC1 DIV, but
on B0 they are parallel with NIC1 DIV. So now the dividers are independent.
This patch modifies the scg_nic_get_rate function according to this change.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-imx/mx7ulp/scg.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index 0d31352c77b..819c90af6ce 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -352,7 +352,7 @@ static u32 scg_ddr_get_rate(void) static u32 scg_nic_get_rate(enum scg_clk clk) { - u32 reg, val, rate; + u32 reg, val, rate, nic0_rate; u32 shift, mask; reg = readl(&scg1_regs->niccsr); @@ -370,6 +370,7 @@ static u32 scg_nic_get_rate(enum scg_clk clk) val = (reg & SCG_NICCSR_NIC0DIV_MASK) >> SCG_NICCSR_NIC0DIV_SHIFT; rate = rate / (val + 1); + nic0_rate = rate; clk_debug("scg_nic_get_rate NIC0 rate %u\n", rate); @@ -411,6 +412,13 @@ static u32 scg_nic_get_rate(enum scg_clk clk) return 0; } + /* + * On RevB, the nic_bus and nic_ext dividers are parallel + * not chained with nic div + */ + if (soc_rev() >= CHIP_REV_2_0) + rate = nic0_rate; + val = (reg & mask) >> shift; rate = rate / (val + 1); |