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authorSuman Anna <s-anna@ti.com>2016-03-04 10:36:39 -0600
committerTom Rini <trini@konsulko.com>2016-03-14 19:18:43 -0400
commitf2a8279e7647411cfdd694daec7903d60da5a36f (patch)
tree7a949a13ece13e520f0e2dbe43dbdb12a8d713aa /arch/arm
parent4ed8b2c969932ec0346b157f0d53173ff52a97c1 (diff)
ARM: keystone2: K2G: power-off DSP during boot
The DSPs are powered on by default upon a Power ON reset, and they are powered off on current Keystone 2 SoCs - K2HK, K2L, K2E during the boot in u-boot. This is not functional on K2G though. Extend the existing DSP power-off support to the only DSP present on K2G. Do note that the PSC clock domain module id for DSP on K2G differs from that of previous Keystone2 SoCs. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-keystone/include/mach/hardware-k2g.h7
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
index fa4162fe99..ca2a119d39 100644
--- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
@@ -10,7 +10,7 @@
#ifndef __ASM_ARCH_HARDWARE_K2G_H
#define __ASM_ARCH_HARDWARE_K2G_H
-#define KS2_NUM_DSPS 0
+#define KS2_NUM_DSPS 1
/* Power and Sleep Controller (PSC) Domains */
#define KS2_LPSC_ALWAYSON 0
@@ -30,7 +30,10 @@
#define KS2_LPSC_MCASP 15
#define KS2_LPSC_SR 16
#define KS2_LPSC_MSMC 17
-#define KS2_LPSC_GEM 18
+#ifdef KS2_LPSC_GEM_0
+#undef KS2_LPSC_GEM_0
+#endif
+#define KS2_LPSC_GEM_0 18
#define KS2_LPSC_ARM 19
#define KS2_LPSC_ASRC 20
#define KS2_LPSC_ICSS 21