diff options
author | Stefan Agner <stefan.agner@toradex.com> | 2014-07-17 16:28:37 +0200 |
---|---|---|
committer | Stefan Agner <stefan.agner@toradex.com> | 2014-10-23 11:10:58 +0200 |
commit | af7c111153cbe14f763bea89b7db60cac710bcbe (patch) | |
tree | 5157fac022194c543c4f222033f66ee64713d222 /arch/arm | |
parent | b16eb3e299d15577c18531223ff91ae225d21b4b (diff) |
vf610: enable external 32KHz oscillator
Enable the SCSC (Slow Clock Source Controller) and select the
external 32KHz oscillator. This improves accuracy of the RTC.
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/include/asm/arch-vf610/crm_regs.h | 1 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-vf610/imx-regs.h | 11 |
2 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 724682c683c..64854fd8a4b 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -199,6 +199,7 @@ struct anadig_reg { #define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24) #define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26) #define CCM_CCGR3_ANADIG_CTRL_MASK 0x3 +#define CCM_CCGR3_SCSC_CTRL_MASK (0x3 << 4) #define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20) #define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22) #define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 6c76aef1d75..6c7c2d83db1 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -65,7 +65,7 @@ #define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000) #define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000) #define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000) -#define SCSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000) +#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000) #define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000) #define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000) #define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000) @@ -258,6 +258,9 @@ #define DDRMC_CR161_TODTH_RD(v) (((v) & 0xf) << 8) #define DDRMC_CR161_TODTH_WR(v) ((v) & 0xf) +/* Slow Clock Source Controller Module (SCSC) */ +#define SCSC_SOSC_CTR_SOSC_EN (0x1) + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> @@ -454,6 +457,12 @@ struct mscm { u32 cpxcfg3; }; +/* SCSC */ +struct scsc_reg { + u32 sirc_ctr; + u32 sosc_ctr; +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_IMX_REGS_H__ */ |