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authorOtavio Salvador <otavio@ossystems.com.br>2012-08-13 09:53:12 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-09-01 14:58:25 +0200
commitfa7a51cb8272bd6076ea4701fd6bdc65a68703ba (patch)
treeb1dd7f9cc3921fb5eb1cd0cbd9a34b1e197f7ae9 /arch/arm
parentaf963ba8f4f301475d13faa42b5dec8f0ed3c23a (diff)
mxs: Convert sys_proto.h prefixes to 'mxs'
The sys_proto.h functions (except the boot modes) are compatible with i.MX233 and i.MX28 so we use 'mxs' prefix for its methods. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/mxs.c32
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/spl_boot.c6
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/timer.c2
-rw-r--r--arch/arm/include/asm/arch-mxs/sys_proto.h20
4 files changed, 30 insertions, 30 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index a61f75be8c..c028e5ea1c 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -41,8 +41,8 @@ DECLARE_GLOBAL_DATA_PTR;
/* 1 second delay should be plenty of time for block reset. */
#define RESET_MAX_TIMEOUT 1000000
-#define MX28_BLOCK_SFTRST (1 << 31)
-#define MX28_BLOCK_CLKGATE (1 << 30)
+#define MXS_BLOCK_SFTRST (1 << 31)
+#define MXS_BLOCK_CLKGATE (1 << 30)
/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
inline void lowlevel_init(void) {}
@@ -81,7 +81,7 @@ void enable_caches(void)
#endif
}
-int mx28_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout)
+int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout)
{
while (--timeout) {
if ((readl(&reg->reg) & mask) == mask)
@@ -92,7 +92,7 @@ int mx28_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout)
return !timeout;
}
-int mx28_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout)
+int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout)
{
while (--timeout) {
if ((readl(&reg->reg) & mask) == 0)
@@ -103,34 +103,34 @@ int mx28_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout)
return !timeout;
}
-int mx28_reset_block(struct mxs_register_32 *reg)
+int mxs_reset_block(struct mxs_register_32 *reg)
{
/* Clear SFTRST */
- writel(MX28_BLOCK_SFTRST, &reg->reg_clr);
+ writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
- if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
return 1;
/* Clear CLKGATE */
- writel(MX28_BLOCK_CLKGATE, &reg->reg_clr);
+ writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
/* Set SFTRST */
- writel(MX28_BLOCK_SFTRST, &reg->reg_set);
+ writel(MXS_BLOCK_SFTRST, &reg->reg_set);
/* Wait for CLKGATE being set */
- if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+ if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
return 1;
/* Clear SFTRST */
- writel(MX28_BLOCK_SFTRST, &reg->reg_clr);
+ writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
- if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
return 1;
/* Clear CLKGATE */
- writel(MX28_BLOCK_CLKGATE, &reg->reg_clr);
+ writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
- if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
return 1;
return 0;
@@ -229,7 +229,7 @@ int print_cpuinfo(void)
get_cpu_type(),
get_cpu_rev(),
mxc_get_clock(MXC_ARM_CLK) / 1000000);
- printf("BOOT: %s\n", mx28_boot_modes[data->boot_mode_idx].mode);
+ printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
return 0;
}
#endif
@@ -299,7 +299,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
- if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
+ if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
MXS_OCOTP_MAX_TIMEOUT)) {
printf("MXS FEC: Can't get MAC from OCOTP\n");
return;
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index 84d4a17d65..ddafddbf2b 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -82,9 +82,9 @@ uint8_t mxs_get_bootmode_index(void)
bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4;
bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
- for (i = 0; i < ARRAY_SIZE(mx28_boot_modes); i++) {
- masked = bootmode & mx28_boot_modes[i].boot_mask;
- if (masked == mx28_boot_modes[i].boot_pads)
+ for (i = 0; i < ARRAY_SIZE(mxs_boot_modes); i++) {
+ masked = bootmode & mxs_boot_modes[i].boot_mask;
+ if (masked == mxs_boot_modes[i].boot_pads)
break;
}
diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c
index c4b0f5e26e..4ed75e604c 100644
--- a/arch/arm/cpu/arm926ejs/mxs/timer.c
+++ b/arch/arm/cpu/arm926ejs/mxs/timer.c
@@ -66,7 +66,7 @@ int timer_init(void)
(struct mxs_timrot_regs *)MXS_TIMROT_BASE;
/* Reset Timers and Rotary Encoder module */
- mx28_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
+ mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
/* Set fixed_count to 0 */
writel(0, &timrot_regs->hw_timrot_fixed_count0);
diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h
index 91645ebbb0..9d1e5999da 100644
--- a/arch/arm/include/asm/arch-mxs/sys_proto.h
+++ b/arch/arm/include/asm/arch-mxs/sys_proto.h
@@ -1,5 +1,5 @@
/*
- * Freescale i.MX28 MX28 specific functions
+ * Freescale i.MX233/i.MX28 specific functions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
@@ -20,14 +20,14 @@
*
*/
-#ifndef __MX28_H__
-#define __MX28_H__
+#ifndef __SYS_PROTO_H__
+#define __SYS_PROTO_H__
-int mx28_reset_block(struct mxs_register_32 *reg);
-int mx28_wait_mask_set(struct mxs_register_32 *reg,
+int mxs_reset_block(struct mxs_register_32 *reg);
+int mxs_wait_mask_set(struct mxs_register_32 *reg,
uint32_t mask,
int timeout);
-int mx28_wait_mask_clr(struct mxs_register_32 *reg,
+int mxs_wait_mask_clr(struct mxs_register_32 *reg,
uint32_t mask,
int timeout);
@@ -39,13 +39,13 @@ void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
const unsigned int iomux_size);
#endif
-struct mx28_pair {
+struct mxs_pair {
uint8_t boot_pads;
uint8_t boot_mask;
const char *mode;
};
-static const struct mx28_pair mx28_boot_modes[] = {
+static const struct mxs_pair mxs_boot_modes[] = {
{ 0x00, 0x0f, "USB #0" },
{ 0x01, 0x1f, "I2C #0, master, 3V3" },
{ 0x11, 0x1f, "I2C #0, master, 1V8" },
@@ -69,6 +69,6 @@ struct mxs_spl_data {
uint32_t mem_dram_size;
};
-int mx28_dram_init(void);
+int mxs_dram_init(void);
-#endif /* __MX28_H__ */
+#endif /* __SYS_PROTO_H__ */