arm: Tegra3: update T30 clock_and_reset controller support

Signed-off-by: Tom Warren <twarren@nvidia.com>

BUG=chromium-os:21033
TEST=built Seaboard & Waluigi OK. Booted my Waluigi to cmd prompt OK.
MMC, SPI and I2C still work fine, as does UART.

More can be done at a later date to cleanup AP20.c for T30 (and
rename/move it, since AP20 is a T2x name) and use new T30 V/W clock
enables/resets/sources/etc.

Change-Id: Ia3a86c519481fffde6926e1fece1dcf898d199c9
Reviewed-on: https://gerrit.chromium.org/gerrit/11911
Tested-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

8 files changed, 893 insertions, 183 deletions

diff --git a/arch/arm/cpu/armv7/tegra-common/ap20.c b/arch/arm/cpu/armv7/tegra-common/ap20.c
index 40e8f36cff..679277b85e 100644
--- a/arch/arm/cpu/armv7/tegra-common/ap20.c
+++ b/arch/arm/cpu/armv7/tegra-common/ap20.c
@@ -348,6 +348,7 @@ static void reset_A9_cpu(int reset)
  */
 void t30_init_clocks(void)
 {
+#if defined(CONFIG_TEGRA3)
 	/*
 	* Sadly our clock functions don't support the V and W clocks of T30
 	* yet, as well as a few other functions, so use low-level register
@@ -385,17 +386,16 @@ void t30_init_clocks(void)
 	/* Put i2c, mselect in reset and enable clocks */
 	reset_set_enable(PERIPH_ID_DVC_I2C, 1);
 	clock_set_enable(PERIPH_ID_DVC_I2C, 1);
-	setbits_le32(&clkrst->crc_clk_out_enb_v, 1 << 3);
+	reset_set_enable(PERIPH_ID_MSELECT, 1);
+	clock_set_enable(PERIPH_ID_MSELECT, 1);
 
-	/* Switch MSELECT clock to PLLP */
-	val = readl(&clkrst->crc_clk_source_mselect);
-	val &= ~MSELECT_CLK_M_MASK;
-	writel(val, &clkrst->crc_clk_source_mselect);
+	/* Switch MSELECT clock to PLLP (00) */
+	clock_ll_set_source(PERIPH_ID_MSELECT, 0);
 
 	/*
 	 * Our high-level clock routines are not available prior to
 	 * relocation. We use the low-level functions which require a
-	 * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17
+	 * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)
 	 */
 	clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16);
 
@@ -405,7 +405,8 @@ void t30_init_clocks(void)
 	 */
 	udelay(1000);
 	reset_set_enable(PERIPH_ID_DVC_I2C, 0);
-	clrbits_le32(&clkrst->crc_rst_devices_v, 1 << 3);
+	reset_set_enable(PERIPH_ID_MSELECT, 0);
+#endif	/* CONFIG_TEGRA3 */
 }
 
 static void clock_enable_coresight(int enable)
diff --git a/arch/arm/cpu/armv7/tegra-common/clock.c b/arch/arm/cpu/armv7/tegra-common/clock.c
index e0d2750193..65f74fcbc4 100644
--- a/arch/arm/cpu/armv7/tegra-common/clock.c
+++ b/arch/arm/cpu/armv7/tegra-common/clock.c
@@ -19,8 +19,9 @@
  * MA 02111-1307 USA
  */
 
-/* Tegra2 Clock control functions */
+/* Tegra Clock control functions */
 
+#include <common.h>
 #include <asm/io.h>
 #include <asm/arch-tegra/ap20.h>
 #include <asm/arch-tegra/bitfield.h>
@@ -28,7 +29,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/timer.h>
 #include <asm/arch/tegra.h>
-#include <common.h>
 #include <div64.h>
 
 /*
@@ -50,7 +50,7 @@ static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
 };
 
 /*
- * Clock types that we can use as a source. The Tegra2 has muxes for the
+ * Clock types that we can use as a source. Tegra has muxes for the
  * peripheral clocks, and in most cases there are four options for the clock
  * source. This gives us a clock 'type' and exploits what commonality exists
  * in the device.
@@ -71,7 +71,9 @@ enum clock_type_id {
 	CLOCK_TYPE_PCMT,
 	CLOCK_TYPE_PCXTS,
 	CLOCK_TYPE_PDCT,
-
+#if defined(CONFIG_TEGRA3)
+	CLOCK_TYPE_ACPT,
+#endif
 	CLOCK_TYPE_COUNT,
 	CLOCK_TYPE_NONE = -1,	/* invalid clock type */
 };
@@ -119,6 +121,112 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT] [CLOCK_MAX_MUX] = {
  */
 enum periphc_internal_id {
 	/* 0x00 */
+#if defined(CONFIG_TEGRA3)
+	PERIPHC_I2S1,
+	PERIPHC_I2S2,
+	PERIPHC_SPDIF_OUT,
+	PERIPHC_SPDIF_IN,
+	PERIPHC_PWM,
+	PERIPHC_05h,
+	PERIPHC_SBC2,
+	PERIPHC_SBC3,
+
+	/* 0x08 */
+	PERIPHC_08h,
+	PERIPHC_I2C1,
+	PERIPHC_DVC_I2C,
+	PERIPHC_0bh,
+	PERIPHC_0ch,
+	PERIPHC_SBC1,
+	PERIPHC_DISP1,
+	PERIPHC_DISP2,
+
+	/* 0x10 */
+	PERIPHC_CVE,
+	PERIPHC_11h,
+	PERIPHC_VI,
+	PERIPHC_13h,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC2,
+	PERIPHC_G3D,
+	PERIPHC_G2D,
+
+	/* 0x18 */
+	PERIPHC_NDFLASH,
+	PERIPHC_SDMMC4,
+	PERIPHC_VFIR,
+	PERIPHC_EPP,
+	PERIPHC_MPE,
+	PERIPHC_MIPI,
+	PERIPHC_UART1,
+	PERIPHC_UART2,
+
+	/* 0x20 */
+	PERIPHC_HOST1X,
+	PERIPHC_21h,
+	PERIPHC_TVO,
+	PERIPHC_HDMI,
+	PERIPHC_24h,
+	PERIPHC_TVDAC,
+	PERIPHC_I2C2,
+	PERIPHC_EMC,
+
+	/* 0x28 */
+	PERIPHC_UART3,
+	PERIPHC_29h,
+	PERIPHC_VI_SENSOR,
+	PERIPHC_2bh,
+	PERIPHC_2ch,
+	PERIPHC_SBC4,
+	PERIPHC_I2C3,
+	PERIPHC_SDMMC3,
+
+	/* 0x30 */
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_VDE,
+	PERIPHC_OWR,
+	PERIPHC_NOR,
+	PERIPHC_CSITE,
+	PERIPHC_I2S0,
+	PERIPHC_37h,
+
+	PERIPHC_VW_FIRST,
+	/* 0x38 */
+	PERIPHC_G3D2 = PERIPHC_VW_FIRST,
+	PERIPHC_MSELECT,
+	PERIPHC_TSENSOR,
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+
+	/* 0x40 */
+	PERIPHC_AUDIO,
+	PERIPHC_41h,
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+	PERIPHC_ACTMON,
+	PERIPHC_EXTPERIPH1,
+
+	/* 0x48 */
+	PERIPHC_EXTPERIPH2,
+	PERIPHC_EXTPERIPH3,
+	PERIPHC_NANDSPEED,
+	PERIPHC_I2CSLOW,
+	PERIPHC_SYS,
+	PERIPHC_SPEEDO,
+	PERIPHC_4eh,
+	PERIPHC_4fh,
+
+	/* 0x50 */
+	PERIPHC_SATAOOB,
+	PERIPHC_SATA,
+	PERIPHC_HDA,
+#else	/* TEGRA2 */
 	PERIPHC_I2S1,
 	PERIPHC_I2S2,
 	PERIPHC_SPDIF_OUT,
@@ -186,6 +294,7 @@ enum periphc_internal_id {
 	PERIPHC_NOR,
 	PERIPHC_CSITE,
 
+#endif
 	PERIPHC_COUNT,
 
 	PERIPHC_NONE = -1,
@@ -202,6 +311,111 @@ enum periphc_internal_id {
 #define TYPE(name, type) type
 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
 	/* 0x00 */
+#if defined(CONFIG_TEGRA3)
+	TYPE(PERIPHC_I2S1,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S2,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_OUT,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_IN,	CLOCK_TYPE_PCM),
+	TYPE(PERIPHC_PWM,	CLOCK_TYPE_PCXTS),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC2,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SBC3,	CLOCK_TYPE_PCMT),
+
+	/* 0x08 */
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_I2C1,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_DVC_I2C,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC1,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_DISP1,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_DISP2,	CLOCK_TYPE_PDCT),
+
+	/* 0x10 */
+	TYPE(PERIPHC_CVE,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SDMMC1,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SDMMC2,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_G3D,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_G2D,	CLOCK_TYPE_MCPA),
+
+	/* 0x18 */
+	TYPE(PERIPHC_NDFLASH,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SDMMC4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_VFIR,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_EPP,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MPE,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MIPI,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_UART1,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_UART2,	CLOCK_TYPE_PCMT),
+
+	/* 0x20 */
+	TYPE(PERIPHC_HOST1X,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_TVO,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_HDMI,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_TVDAC,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_I2C2,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_EMC,	CLOCK_TYPE_MCPT),
+
+	/* 0x28 */
+	TYPE(PERIPHC_UART3,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2C3,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SDMMC3,	CLOCK_TYPE_PCMT),
+
+	/* 0x30 */
+	TYPE(PERIPHC_UART4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_UART5,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_VDE,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_OWR,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NOR,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_CSITE,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2S0,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+
+	/* 0x38h */
+	TYPE(PERIPHC_G3D2,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MSELECT,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_TSENSOR,	CLOCK_TYPE_PCM),
+	TYPE(PERIPHC_I2S3,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S4,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2C4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SBC5,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SBC6,	CLOCK_TYPE_PCMT),
+
+	/* 0x40 */
+	TYPE(PERIPHC_AUDIO,	CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_DAM0,	CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_DAM1,	CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_DAM2,	CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_ACTMON,	CLOCK_TYPE_PCM),
+	TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_PCXTS),
+
+	/* 0x48 */
+	TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_PCXTS),
+	TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_PCXTS),
+	TYPE(PERIPHC_NANDSPEED,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2CSLOW,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SYS,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SPEEDO,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+
+	/* 0x50 */
+	TYPE(PERIPHC_SATAOOB,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SATA,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_HDA,	CLOCK_TYPE_PCMT),
+#else	/* Tegra2 */
 	TYPE(PERIPHC_I2S1,	CLOCK_TYPE_AXPT),
 	TYPE(PERIPHC_I2S2,	CLOCK_TYPE_AXPT),
 	TYPE(PERIPHC_SPDIF_OUT,	CLOCK_TYPE_AXPT),
@@ -268,6 +482,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
 	TYPE(PERIPHC_OWR,	CLOCK_TYPE_PCMT),
 	TYPE(PERIPHC_NOR,	CLOCK_TYPE_PCMT),
 	TYPE(PERIPHC_CSITE,	CLOCK_TYPE_PCMT),
+#endif
 };
 
 /*
@@ -275,13 +490,193 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
  *
  * Not present/matched up:
  *	uint vi_sensor;	 _VI_SENSOR_0,		0x1A8
- * 	SPDIF - which is both 0x08 and 0x0c
+ *	SPDIF - which is both 0x08 and 0x0c
  *
  */
 #define NONE(name) (-1)
 #define OFFSET(name, value) PERIPHC_ ## name
 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
 	/* Low word: 31:0 */
+#if defined(CONFIG_TEGRA3)
+	NONE(CPU),
+	NONE(COP),
+	NONE(TRIGSYS),
+	NONE(RESERVED3),
+	NONE(RESERVED4),
+	NONE(TMR),
+	PERIPHC_UART1,
+	PERIPHC_UART2,	/* and vfir 0x68 */
+
+	/* 8 */
+	NONE(GPIO),
+	PERIPHC_SDMMC2,
+	NONE(SPDIF),		/* 0x08 and 0x0c, unclear which to use */
+	PERIPHC_I2S1,
+	PERIPHC_I2C1,
+	PERIPHC_NDFLASH,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC4,
+
+	/* 16 */
+	NONE(RESERVED16),
+	PERIPHC_PWM,
+	PERIPHC_I2S2,
+	PERIPHC_EPP,
+	PERIPHC_VI,
+	PERIPHC_G2D,
+	NONE(USBD),
+	NONE(ISP),
+
+	/* 24 */
+	PERIPHC_G3D,
+	NONE(RESERVED25),
+	PERIPHC_DISP2,
+	PERIPHC_DISP1,
+	PERIPHC_HOST1X,
+	NONE(VCP),
+	PERIPHC_I2S0,
+	NONE(CACHE2),
+
+	/* Middle word: 63:32 */
+	NONE(MEM),
+	NONE(AHBDMA),
+	NONE(APBDMA),
+	NONE(RESERVED35),
+	NONE(RESERVED36),
+	NONE(STAT_MON),
+	NONE(RESERVED38),
+	NONE(RESERVED39),
+
+	/* 40 */
+	NONE(KFUSE),
+	NONE(SBC1),	/* SBC1, 0x34, is this SPI1? */
+	PERIPHC_NOR,
+	NONE(RESERVED43),
+	PERIPHC_SBC2,
+	NONE(RESERVED45),
+	PERIPHC_SBC3,
+	PERIPHC_DVC_I2C,
+
+	/* 48 */
+	NONE(DSI),
+	PERIPHC_TVO,	/* also CVE 0x40 */
+	PERIPHC_MIPI,
+	PERIPHC_HDMI,
+	NONE(CSI),
+	PERIPHC_TVDAC,
+	PERIPHC_I2C2,
+	PERIPHC_UART3,
+
+	/* 56 */
+	NONE(RESERVED56),
+	PERIPHC_EMC,
+	NONE(USB2),
+	NONE(USB3),
+	PERIPHC_MPE,
+	PERIPHC_VDE,
+	NONE(BSEA),
+	NONE(BSEV),
+
+	/* Upper word 95:64 */
+	PERIPHC_SPEEDO,
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_I2C3,
+	PERIPHC_SBC4,
+	PERIPHC_SDMMC3,
+	NONE(PCIE),
+	PERIPHC_OWR,
+
+	/* 72 */
+	NONE(AFI),
+	PERIPHC_CSITE,
+	NONE(PCIEXCLK),
+	NONE(AVPUCQ),
+	NONE(RESERVED76),
+	NONE(RESERVED77),
+	NONE(RESERVED78),
+	NONE(DTV),
+
+	/* 80 */
+	PERIPHC_NANDSPEED,
+	PERIPHC_I2CSLOW,
+	NONE(DSIB),
+	NONE(RESERVED83),
+	NONE(IRAMA),
+	NONE(IRAMB),
+	NONE(IRAMC),
+	NONE(IRAMD),
+
+	/* 88 */
+	NONE(CRAM2),
+	NONE(RESERVED89),
+	NONE(MDOUBLER),
+	NONE(RESERVED91),
+	NONE(SUSOUT),
+	NONE(RESERVED93),
+	NONE(RESERVED94),
+	NONE(RESERVED95),
+
+	/* V word: 31:0 */
+	NONE(CPUG),
+	NONE(CPULP),
+	PERIPHC_G3D2,
+	PERIPHC_MSELECT,
+	PERIPHC_TSENSOR,
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+
+	/* 08 */
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+	PERIPHC_AUDIO,
+	NONE(APBIF),
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+
+	/* 16 */
+	NONE(ATOMICS),
+	NONE(RESERVED17),
+	NONE(RESERVED18),
+	NONE(RESERVED19),
+	NONE(RESERVED20),
+	NONE(RESERVED21),
+	NONE(RESERVED22),
+	PERIPHC_ACTMON,
+
+	/* 24 */
+	NONE(RESERVED24),
+	NONE(RESERVED25),
+	NONE(RESERVED26),
+	NONE(RESERVED27),
+	PERIPHC_SATA,
+	PERIPHC_HDA,
+	NONE(RESERVED30),
+	NONE(RESERVED31),
+
+	/* W word: 31:0 */
+	NONE(HDA2HDMICODEC),
+	NONE(SATACOLD),
+	NONE(RESERVED0_PCIERX0),
+	NONE(RESERVED1_PCIERX1),
+	NONE(RESERVED2_PCIERX2),
+	NONE(RESERVED3_PCIERX3),
+	NONE(RESERVED4_PCIERX4),
+	NONE(RESERVED5_PCIERX5),
+
+	/* 40 */
+	NONE(CEC),
+	NONE(RESERVED6_PCIE2),
+	NONE(RESERVED7_EMC),
+	NONE(RESERVED8_HDMI),
+	NONE(RESERVED9_SATA),
+	NONE(RESERVED10_MIPI),
+	NONE(EX_RESERVED46),
+	NONE(EX_RESERVED47),
+#else	/* Tegra2 */
 	NONE(CPU),
 	NONE(RESERVED1),
 	NONE(RESERVED2),
@@ -291,7 +686,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
 	PERIPHC_UART1,
 	PERIPHC_UART2,	/* and vfir 0x68 */
 
-	/* 0x08 */
+	/* 8 */
 	NONE(GPIO),
 	PERIPHC_SDMMC2,
 	NONE(SPDIF),		/* 0x08 and 0x0c, unclear which to use */
@@ -301,7 +696,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
 	PERIPHC_SDMMC1,
 	PERIPHC_SDMMC4,
 
-	/* 0x10 */
+	/* 16 */
 	PERIPHC_TWC,
 	PERIPHC_PWM,
 	PERIPHC_I2S2,
@@ -311,7 +706,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
 	NONE(USBD),
 	NONE(ISP),
 
-	/* 0x18 */
+	/* 24 */
 	PERIPHC_G3D,
 	PERIPHC_IDE0,
 	PERIPHC_DISP2,
@@ -331,7 +726,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
 	NONE(PMC),
 	NONE(FUSE),
 
-	/* 0x28 */
+	/* 40 */
 	NONE(KFUSE),
 	NONE(SBC1),	/* SBC1, 0x34, is this SPI1? */
 	PERIPHC_NOR,
@@ -341,7 +736,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
 	PERIPHC_SPI3,
 	PERIPHC_DVC_I2C,
 
-	/* 0x30 */
+	/* 48 */
 	NONE(DSI),
 	PERIPHC_TVO,	/* also CVE 0x40 */
 	PERIPHC_MIPI,
@@ -351,7 +746,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
 	PERIPHC_I2C2,
 	PERIPHC_UART3,
 
-	/* 0x38 */
+	/* 56 */
 	NONE(RESERVED56),
 	PERIPHC_EMC,
 	NONE(USB2),
@@ -371,7 +766,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
 	NONE(PCIE),
 	PERIPHC_OWR,
 
-	/* 0x48 */
+	/* 72 */
 	NONE(AFI),
 	NONE(CORESIGHT),
 	NONE(RESERVED74),
@@ -381,7 +776,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
 	NONE(RESERVED78),
 	NONE(RESERVED79),
 
-	/* 0x50 */
+	/* 80 */
 	NONE(RESERVED80),
 	NONE(RESERVED81),
 	NONE(RESERVED82),
@@ -391,8 +786,9 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
 	NONE(IRAMC),
 	NONE(IRAMD),
 
-	/* 0x58 */
+	/* 88 */
 	NONE(CRAM2),
+#endif
 };
 
 /*
@@ -457,7 +853,27 @@ static int clock_periph_id_isvalid(enum periph_id id)
 {
 	if (id < PERIPH_ID_FIRST || id >= PERIPH_ID_COUNT)
 		printf("Peripheral id %d out of range\n", id);
-	else switch (id) {
+	else
+	switch (id) {
+#if defined(CONFIG_TEGRA3)
+	case PERIPH_ID_RESERVED3:
+	case PERIPH_ID_RESERVED4:
+	case PERIPH_ID_RESERVED16:
+	case PERIPH_ID_RESERVED24:
+	case PERIPH_ID_RESERVED35:
+	case PERIPH_ID_RESERVED43:
+	case PERIPH_ID_RESERVED45:
+	case PERIPH_ID_RESERVED56:
+	case PERIPH_ID_RESERVED76:
+	case PERIPH_ID_RESERVED77:
+	case PERIPH_ID_RESERVED78:
+	case PERIPH_ID_RESERVED83:
+	case PERIPH_ID_RESERVED89:
+	case PERIPH_ID_RESERVED91:
+	case PERIPH_ID_RESERVED93:
+	case PERIPH_ID_RESERVED94:
+	case PERIPH_ID_RESERVED95:
+#else	/* Tegra2 */
 	case PERIPH_ID_RESERVED1:
 	case PERIPH_ID_RESERVED2:
 	case PERIPH_ID_RESERVED30:
@@ -472,6 +888,7 @@ static int clock_periph_id_isvalid(enum periph_id id)
 	case PERIPH_ID_RESERVED81:
 	case PERIPH_ID_RESERVED82:
 	case PERIPH_ID_RESERVED83:
+#endif
 		printf("Peripheral id %d is reserved\n", id);
 		break;
 	default:
@@ -490,7 +907,13 @@ static u32 *get_periph_source_reg(enum periph_id periph_id)
 	assert(clock_periph_id_isvalid(periph_id));
 	internal_id = periph_id_to_internal_id[periph_id];
 	assert(internal_id != -1);
-	return &clkrst->crc_clk_src[internal_id];
+#if defined(CONFIG_TEGRA3)
+	if (internal_id >= PERIPHC_VW_FIRST) {
+		internal_id -= PERIPHC_VW_FIRST;
+		return &clkrst->crc_clk_src_vw[internal_id];
+	} else
+#endif
+		return &clkrst->crc_clk_src[internal_id];
 }
 
 void clock_ll_set_source_divisor(enum periph_id periph_id, int source,
@@ -551,7 +974,7 @@ static unsigned long get_rate_from_divider(unsigned long parent_rate,
 	u64 rate;
 
 	rate = (u64)parent_rate * 2;
-	do_div (rate, divider + 2);
+	do_div(rate, divider + 2);
 	return rate;
 }
 
@@ -646,7 +1069,7 @@ static int get_periph_clock_source(enum periph_id periph_id,
 	 */
 	assert(type == CLOCK_TYPE_PCXTS);
 	assert(parent == CLOCK_ID_SFROM32KHZ);
-	if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ);
+	if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
 		return 4;	/* mux value for this clock */
 
 	/* if we get here, either us or the caller has made a mistake */
@@ -731,11 +1154,16 @@ void clock_set_enable(enum periph_id periph_id, int enable)
 {
 	struct clk_rst_ctlr *clkrst =
 			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+	u32 *clk;
 	u32 reg;
 
 	/* Enable/disable the clock to this peripheral */
 	assert(clock_periph_id_isvalid(periph_id));
+	clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+#if defined(CONFIG_TEGRA3)
+	if ((int)periph_id >= (int)PERIPH_ID_VW_FIRST)
+		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
+#endif
 	reg = readl(clk);
 	if (enable)
 		reg |= PERIPH_MASK(periph_id);
@@ -758,11 +1186,16 @@ void reset_set_enable(enum periph_id periph_id, int enable)
 {
 	struct clk_rst_ctlr *clkrst =
 			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+	u32 *reset;
 	u32 reg;
 
 	/* Enable/disable reset to the peripheral */
 	assert(clock_periph_id_isvalid(periph_id));
+	reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+#if defined(CONFIG_TEGRA3)
+	if (periph_id >= PERIPH_ID_VW_FIRST)
+		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
+#endif
 	reg = readl(reset);
 	if (enable)
 		reg |= PERIPH_MASK(periph_id);
@@ -835,7 +1268,7 @@ unsigned clock_get_rate(enum clock_id clkid)
  *     where Fo is the output frequency from the PLL.
  * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
  *     216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
- * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
+ * Please see Tegra TRM PLL Programming section to get the details
  *
  * @param n PLL feedback divider(DIVN)
  * @param m PLL input divider(DIVN)
@@ -919,23 +1352,28 @@ void clock_early_init(void)
 {
 	/*
 	 * PLLP output frequency set to 216Mh
-	 * PLLC output frequency set to 600Mhz
-	 *
+	 * PLLC output frequency set to 228Mhz (Tegra3) or 600MHz (Tegra2)
 	 * TODO: Can we calculate these values instead of hard-coding?
 	 */
 	switch (clock_get_osc_freq()) {
 	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
-#ifdef CONFIG_SYS_PLLP_BASE_IS_408MHZ
+#if defined(CONFIG_SYS_PLLP_BASE_IS_408MHZ)
 		clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
 #else
 		clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
-#endif
 		clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
+#endif
 		break;
 
 	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+#if defined(CONFIG_SYS_PLLP_BASE_IS_408MHZ)
+		clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 456, 26, 1, 8);
+#else
 		clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
 		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+#endif
 		break;
 
 	case CLOCK_OSC_FREQ_13_0:
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index 74af2ea8ca..f820581ec7 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -39,6 +39,12 @@ struct clk_pll_simple {
 	uint pll_misc;		/* other misc things */
 };
 
+/* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */
+struct clk_set_clr {
+	uint set;
+	uint clr;
+};
+
 /*
  * Most PLLs use the clk_pll structure, but some have a simpler two-member
  * structure for which we use clk_pll_simple. The reason for this non-
@@ -47,8 +53,10 @@ struct clk_pll_simple {
 enum {
 	TEGRA_CLK_PLLS		= 6,	/* Number of normal PLLs */
 	TEGRA_CLK_SIMPLE_PLLS	= 3,	/* Number of simple PLLs */
-	TEGRA_CLK_REGS		= 3,	/* Number of clock enable registers */
-	TEGRA_CLK_SOURCES	= 64,	/* Number of periph clock sources */
+	TEGRA_CLK_REGS		= 3,	/* Number of clock enable regs L/H/U */
+	TEGRA_CLK_SOURCES	= 64,	/* Number of ppl clock sources L/H/U */
+	TEGRA_CLK_REGS_VW	= 2,	/* Number of clock enable regs V/W */
+	TEGRA_CLK_SOURCES_VW	= 32,	/* Number of ppl clock sources V/W*/
 };
 
 /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@@ -84,30 +92,49 @@ struct clk_rst_ctlr {
 	uint crc_reserved11;		/* _reserved_11,	0xFC */
 
 	uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0...	0x100-1fc */
-	uint crc_reserved20[80];	/*			0x200-33C */
-	uint crc_cpu_cmplx_set;		/* _CPU_CMPLX_SET_0,	0x340	  */
-	uint crc_cpu_cmplx_clr;		/* _CPU_CMPLX_CLR_0,	0x344     */
-
-	/* T30 things */
-	uint crc_clk_cpu_cmplx_set;	/* _CLK_CPU_CMPLX_SET_0, 0x348	  */
-	uint crc_clk_cpu_cmplx_clr;	/* _CLK_CPU_CMPLX_CLR_0, 0x34c    */
-	uint crc_reserved12[2];		/* reserved_12		0x350-354 */
-	uint crc_rst_devices_v;		/* _RST_DEVICES_V	0x358	  */
-	uint crc_rst_devices_w;		/* _RST_DEVICES_W	0x35c	  */
-	uint crc_clk_out_enb_v;		/* _CLK_OUT_ENB_V	0x360	  */
-	uint crc_clk_out_enb_w;		/* _CLK_OUT_ENB_W	0x364	  */
-	uint crc_cclkg_burst_policy;	/* _CCLKG_BURST_POLICY	0x368	  */
-	uint crc_super_cclkg_divider;	/* _SUPER_CCLKG_DIVIDER	0x36c	  */
-	uint crc_cclklp_burst_policy;	/* _CCLKLP_BURST_POLICY	0x370	  */
-	uint crc_super_cclklp_divider;	/* _SUPER_CCLKLP_DIVIDER 0x374	  */
-	uint crc_clk_cpug_cmplx;	/* _CLK_CPUG_CMPLX	0x378	  */
-	uint crc_clk_cpulp_cmplx;	/* _CLK_CPULP_CMPLX	0x37c	  */
-	uint crc_cpu_softrst_ctrl;	/* _CPU_SOFTRST_CTRL	0x380	  */
-	uint crc_reserved13[11];	/* reserved_13		0x384-3ac */
-	uint crc_clk_source_g3d2;	/* _CLK_SOURCE_G3D2	0x3b0	  */
-	uint crc_clk_source_mselect;	/* _CLK_SOURCE_MSELECT	0x3b4	  */
-
-	/* the road goes ever on and on... */
+
+	uint crc_reserved20[64];	/* _reserved_20,	0x200-2fc */
+
+	/* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
+	struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
+
+	uint crc_reserved30[2];		/* _reserved_30,	0x318, 0x31c */
+
+	/* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */
+	struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS];
+
+	uint crc_reserved31[2];		/* _reserved_31,	0x338, 0x33c */
+
+	uint crc_cpu_cmplx_set;		/* _RST_CPU_CMPLX_SET_0,    0x340 */
+	uint crc_cpu_cmplx_clr;		/* _RST_CPU_CMPLX_CLR_0,    0x344 */
+
+	/* Additional (T30) registers */
+	uint crc_clk_cpu_cmplx_set;	/* _CLK_CPU_CMPLX_SET_0,    0x348 */
+	uint crc_clk_cpu_cmplx_clr;	/* _CLK_CPU_CMPLX_SET_0,    0x34c */
+
+	uint crc_reserved32[2];		/* _reserved_32,      0x350,0x354 */
+
+	uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */
+	uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */
+	uint crc_cclkg_brst_pol;	/* _CCLKG_BURST_POLICY_0,   0x368 */
+	uint crc_super_cclkg_div;	/* _SUPER_CCLKG_DIVIDER_0,  0x36C */
+	uint crc_cclklp_brst_pol;	/* _CCLKLP_BURST_POLICY_0,  0x370 */
+	uint crc_super_cclkp_div;	/* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
+	uint crc_clk_cpug_cmplx;	/* _CLK_CPUG_CMPLX_0,       0x378 */
+	uint crc_clk_cpulp_cmplx;	/* _CLK_CPULP_CMPLX_0,      0x37C */
+	uint crc_cpu_softrst_ctrl;	/* _CPU_SOFTRST_CTRL_0,     0x380 */
+	uint crc_reserved33[11];	/* _reserved_33,        0x384-3ac */
+
+	uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */
+	/* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
+	struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
+	/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
+	struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
+
+	uint crc_reserved40[12];	/* _reserved_40,	0x450-47C */
+	uint crc_pll_cfg0;		/* _PLL_CFG0_0,		0x480 */
+	uint crc_pll_cfg1;		/* _PLL_CFG1_0,		0x484 */
+	uint crc_pll_cfg2;		/* _PLL_CFG2_0,		0x488 */
 };
 
 /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index 72050e77a4..7cdfe935ab 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -63,129 +63,6 @@ enum clock_id {
 	CLOCK_ID_NONE = -1,
 };
 
-/* The clocks supported by the hardware */
-enum periph_id {
-	PERIPH_ID_FIRST,
-
-	/* Low word: 31:0 */
-	PERIPH_ID_CPU = PERIPH_ID_FIRST,
-	PERIPH_ID_RESERVED1,
-	PERIPH_ID_RESERVED2,
-	PERIPH_ID_AC97,
-	PERIPH_ID_RTC,
-	PERIPH_ID_TMR,
-	PERIPH_ID_UART1,
-	PERIPH_ID_UART2,
-
-	/* 8 */
-	PERIPH_ID_GPIO,
-	PERIPH_ID_SDMMC2,
-	PERIPH_ID_SPDIF,
-	PERIPH_ID_I2S1,
-	PERIPH_ID_I2C1,
-	PERIPH_ID_NDFLASH,
-	PERIPH_ID_SDMMC1,
-	PERIPH_ID_SDMMC4,
-
-	/* 16 */
-	PERIPH_ID_TWC,
-	PERIPH_ID_PWM,
-	PERIPH_ID_I2S2,
-	PERIPH_ID_EPP,
-	PERIPH_ID_VI,
-	PERIPH_ID_2D,
-	PERIPH_ID_USBD,
-	PERIPH_ID_ISP,
-
-	/* 24 */
-	PERIPH_ID_3D,
-	PERIPH_ID_IDE,
-	PERIPH_ID_DISP2,
-	PERIPH_ID_DISP1,
-	PERIPH_ID_HOST1X,
-	PERIPH_ID_VCP,
-	PERIPH_ID_RESERVED30,
-	PERIPH_ID_CACHE2,
-
-	/* Middle word: 63:32 */
-	PERIPH_ID_MEM,
-	PERIPH_ID_AHBDMA,
-	PERIPH_ID_APBDMA,
-	PERIPH_ID_RESERVED35,
-	PERIPH_ID_KBC,
-	PERIPH_ID_STAT_MON,
-	PERIPH_ID_PMC,
-	PERIPH_ID_FUSE,
-
-	/* 40 */
-	PERIPH_ID_KFUSE,
-	PERIPH_ID_SBC1,
-	PERIPH_ID_SNOR,
-	PERIPH_ID_SPI1,
-	PERIPH_ID_SBC2,
-	PERIPH_ID_XIO,
-	PERIPH_ID_SBC3,
-	PERIPH_ID_DVC_I2C,
-
-	/* 48 */
-	PERIPH_ID_DSI,
-	PERIPH_ID_TVO,
-	PERIPH_ID_MIPI,
-	PERIPH_ID_HDMI,
-	PERIPH_ID_CSI,
-	PERIPH_ID_TVDAC,
-	PERIPH_ID_I2C2,
-	PERIPH_ID_UART3,
-
-	/* 56 */
-	PERIPH_ID_RESERVED56,
-	PERIPH_ID_EMC,
-	PERIPH_ID_USB2,
-	PERIPH_ID_USB3,
-	PERIPH_ID_MPE,
-	PERIPH_ID_VDE,
-	PERIPH_ID_BSEA,
-	PERIPH_ID_BSEV,
-
-	/* Upper word 95:64 */
-	PERIPH_ID_SPEEDO,
-	PERIPH_ID_UART4,
-	PERIPH_ID_UART5,
-	PERIPH_ID_I2C3,
-	PERIPH_ID_SBC4,
-	PERIPH_ID_SDMMC3,
-	PERIPH_ID_PCIE,
-	PERIPH_ID_OWR,
-
-	/* 72 */
-	PERIPH_ID_AFI,
-	PERIPH_ID_CORESIGHT,
-	PERIPH_ID_RESERVED74,
-	PERIPH_ID_AVPUCQ,
-	PERIPH_ID_RESERVED76,
-	PERIPH_ID_RESERVED77,
-	PERIPH_ID_RESERVED78,
-	PERIPH_ID_RESERVED79,
-
-	/* 80 */
-	PERIPH_ID_RESERVED80,
-	PERIPH_ID_RESERVED81,
-	PERIPH_ID_RESERVED82,
-	PERIPH_ID_RESERVED83,
-	PERIPH_ID_IRAMA,
-	PERIPH_ID_IRAMB,
-	PERIPH_ID_IRAMC,
-	PERIPH_ID_IRAMD,
-
-	/* 88 */
-	PERIPH_ID_CRAM2,
-
-	PERIPH_ID_COUNT,
-};
-
-/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
-#define PERIPH_REG(id) ((id) >> 5)
-
 /* Mask value for a clock (within PERIPH_REG(id)) */
 #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
 
@@ -265,7 +142,7 @@ enum crc_reset_id {
 /**
  * Put parts of the CPU complex into or out of reset.\
  *
- * @param cpu		cpu number (0-3)
+ * @param cpu		cpu number (0 ~ 1 on Tegra2, 0 - 3 on Tegra3)
  * @param which		which parts of the complex to affect (OR of crc_reset_id)
  * @param reset		1 to assert reset, 0 to de-assert
  */
@@ -365,4 +242,3 @@ void clock_init(void);
 void clock_early_init(void);
 
 #endif
-
diff --git a/arch/arm/include/asm/arch-tegra2/clock-tables.h b/arch/arm/include/asm/arch-tegra2/clock-tables.h
new file mode 100644
index 0000000000..12cbe6d101
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/clock-tables.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Tegra2 clock tables */
+
+#ifndef _CLOCK_TABLES_H
+#define _CLOCK_TABLES_H
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) ((id) >> 5)
+
+/* The clocks supported by the hardware */
+enum periph_id {
+	PERIPH_ID_FIRST,
+	PERIPH_ID_CPU = PERIPH_ID_FIRST,
+	PERIPH_ID_RESERVED1,
+	PERIPH_ID_RESERVED2,
+	PERIPH_ID_AC97,
+	PERIPH_ID_RTC,
+	PERIPH_ID_TMR,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+
+	/* 8 */
+	PERIPH_ID_GPIO,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_SPDIF,
+	PERIPH_ID_I2S1,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_NDFLASH,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC4,
+
+	/* 16 */
+	PERIPH_ID_TWC,
+	PERIPH_ID_PWM,
+	PERIPH_ID_I2S2,
+	PERIPH_ID_EPP,
+	PERIPH_ID_VI,
+	PERIPH_ID_2D,
+	PERIPH_ID_USBD,
+	PERIPH_ID_ISP,
+
+	/* 24 */
+	PERIPH_ID_3D,
+	PERIPH_ID_IDE,
+	PERIPH_ID_DISP2,
+	PERIPH_ID_DISP1,
+	PERIPH_ID_HOST1X,
+	PERIPH_ID_VCP,
+	PERIPH_ID_RESERVED30,
+	PERIPH_ID_CACHE2,
+
+	/* Middle word: 63:32 */
+	PERIPH_ID_MEM,
+	PERIPH_ID_AHBDMA,
+	PERIPH_ID_APBDMA,
+	PERIPH_ID_RESERVED35,
+	PERIPH_ID_KBC,
+	PERIPH_ID_STAT_MON,
+	PERIPH_ID_PMC,
+	PERIPH_ID_FUSE,
+
+	/* 40 */
+	PERIPH_ID_KFUSE,
+	PERIPH_ID_SBC1,
+	PERIPH_ID_SNOR,
+	PERIPH_ID_SPI1,
+	PERIPH_ID_SBC2,
+	PERIPH_ID_XIO,
+	PERIPH_ID_SBC3,
+	PERIPH_ID_DVC_I2C,
+
+	/* 48 */
+	PERIPH_ID_DSI,
+	PERIPH_ID_TVO,
+	PERIPH_ID_MIPI,
+	PERIPH_ID_HDMI,
+	PERIPH_ID_CSI,
+	PERIPH_ID_TVDAC,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_UART3,
+
+	/* 56 */
+	PERIPH_ID_RESERVED56,
+	PERIPH_ID_EMC,
+	PERIPH_ID_USB2,
+	PERIPH_ID_USB3,
+	PERIPH_ID_MPE,
+	PERIPH_ID_VDE,
+	PERIPH_ID_BSEA,
+	PERIPH_ID_BSEV,
+
+	/* Upper word 95:64 */
+	PERIPH_ID_SPEEDO,
+	PERIPH_ID_UART4,
+	PERIPH_ID_UART5,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_SBC4,
+	PERIPH_ID_SDMMC3,
+	PERIPH_ID_PCIE,
+	PERIPH_ID_OWR,
+
+	/* 72 */
+	PERIPH_ID_AFI,
+	PERIPH_ID_CORESIGHT,
+	PERIPH_ID_RESERVED74,
+	PERIPH_ID_AVPUCQ,
+	PERIPH_ID_RESERVED76,
+	PERIPH_ID_RESERVED77,
+	PERIPH_ID_RESERVED78,
+	PERIPH_ID_RESERVED79,
+
+	/* 80 */
+	PERIPH_ID_RESERVED80,
+	PERIPH_ID_RESERVED81,
+	PERIPH_ID_RESERVED82,
+	PERIPH_ID_RESERVED83,
+	PERIPH_ID_IRAMA,
+	PERIPH_ID_IRAMB,
+	PERIPH_ID_IRAMC,
+	PERIPH_ID_IRAMD,
+
+	/* 88 */
+	PERIPH_ID_CRAM2,
+
+	PERIPH_ID_COUNT,
+};
+#endif	/* _CLOCK_TABLES_H */
diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra2/clock.h
index c11066760e..914f721725 100644
--- a/arch/arm/include/asm/arch-tegra2/clock.h
+++ b/arch/arm/include/asm/arch-tegra2/clock.h
@@ -19,4 +19,5 @@
  * MA 02111-1307 USA
  */
 
+#include "asm/arch/clock-tables.h"
 #include "asm/arch-tegra/clock.h"
diff --git a/arch/arm/include/asm/arch-tegra3/clock-tables.h b/arch/arm/include/asm/arch-tegra3/clock-tables.h
new file mode 100644
index 0000000000..1a6939997f
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra3/clock-tables.h
@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Tegra3 clock tables */
+
+#ifndef _CLOCK_TABLES_H
+#define _CLOCK_TABLES_H
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+	(id < PERIPH_ID_VW_FIRST) ? \
+		((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* The clocks supported by the hardware */
+enum periph_id {
+	PERIPH_ID_FIRST,
+	/* Low word: 31:0 */
+	PERIPH_ID_CPU = PERIPH_ID_FIRST,
+	PERIPH_ID_COP,
+	PERIPH_ID_TRIGSYS,
+	PERIPH_ID_RESERVED3,
+	PERIPH_ID_RESERVED4,
+	PERIPH_ID_TMR,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+
+	/* 8 */
+	PERIPH_ID_GPIO,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_SPDIF,
+	PERIPH_ID_I2S1,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_NDFLASH,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC4,
+
+	/* 16 */
+	PERIPH_ID_RESERVED16,
+	PERIPH_ID_PWM,
+	PERIPH_ID_I2S2,
+	PERIPH_ID_EPP,
+	PERIPH_ID_VI,
+	PERIPH_ID_2D,
+	PERIPH_ID_USBD,
+	PERIPH_ID_ISP,
+
+	/* 24 */
+	PERIPH_ID_3D,
+	PERIPH_ID_RESERVED24,
+	PERIPH_ID_DISP2,
+	PERIPH_ID_DISP1,
+	PERIPH_ID_HOST1X,
+	PERIPH_ID_VCP,
+	PERIPH_ID_I2S0,
+	PERIPH_ID_CACHE2,
+
+	/* Middle word: 63:32 */
+	PERIPH_ID_MEM,
+	PERIPH_ID_AHBDMA,
+	PERIPH_ID_APBDMA,
+	PERIPH_ID_RESERVED35,
+	PERIPH_ID_KBC,
+	PERIPH_ID_STAT_MON,
+	PERIPH_ID_PMC,
+	PERIPH_ID_FUSE,
+
+	/* 40 */
+	PERIPH_ID_KFUSE,
+	PERIPH_ID_SBC1,
+	PERIPH_ID_SNOR,
+	PERIPH_ID_RESERVED43,
+	PERIPH_ID_SBC2,
+	PERIPH_ID_RESERVED45,
+	PERIPH_ID_SBC3,
+	PERIPH_ID_DVC_I2C,
+
+	/* 48 */
+	PERIPH_ID_DSI,
+	PERIPH_ID_TVO,
+	PERIPH_ID_MIPI,
+	PERIPH_ID_HDMI,
+	PERIPH_ID_CSI,
+	PERIPH_ID_TVDAC,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_UART3,
+
+	/* 56 */
+	PERIPH_ID_RESERVED56,
+	PERIPH_ID_EMC,
+	PERIPH_ID_USB2,
+	PERIPH_ID_USB3,
+	PERIPH_ID_MPE,
+	PERIPH_ID_VDE,
+	PERIPH_ID_BSEA,
+	PERIPH_ID_BSEV,
+
+	/* Upper word 95:64 */
+	PERIPH_ID_SPEEDO,
+	PERIPH_ID_UART4,
+	PERIPH_ID_UART5,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_SBC4,
+	PERIPH_ID_SDMMC3,
+	PERIPH_ID_PCIE,
+	PERIPH_ID_OWR,
+
+	/* 72 */
+	PERIPH_ID_AFI,
+	PERIPH_ID_CORESIGHT,
+	PERIPH_ID_PCIEXCLK,
+	PERIPH_ID_AVPUCQ,
+	PERIPH_ID_RESERVED76,
+	PERIPH_ID_RESERVED77,
+	PERIPH_ID_RESERVED78,
+	PERIPH_ID_DTV,
+
+	/* 80 */
+	PERIPH_ID_NANDSPEED,
+	PERIPH_ID_I2CSLOW,
+	PERIPH_ID_DSIB,
+	PERIPH_ID_RESERVED83,
+	PERIPH_ID_IRAMA,
+	PERIPH_ID_IRAMB,
+	PERIPH_ID_IRAMC,
+	PERIPH_ID_IRAMD,
+
+	/* 88 */
+	PERIPH_ID_CRAM2,
+	PERIPH_ID_RESERVED89,
+	PERIPH_ID_MDOUBLER,
+	PERIPH_ID_RESERVED91,
+	PERIPH_ID_SUSOUT,
+	PERIPH_ID_RESERVED93,
+	PERIPH_ID_RESERVED94,
+	PERIPH_ID_RESERVED95,
+
+	PERIPH_ID_VW_FIRST,
+	/* V word: 31:0 */
+	PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+	PERIPH_ID_CPULP,
+	PERIPH_ID_3D2,
+	PERIPH_ID_MSELECT,
+	PERIPH_ID_TSENSOR,
+	PERIPH_ID_I2S3,
+	PERIPH_ID_I2S4,
+	PERIPH_ID_I2C4,
+
+	/* 08 */
+	PERIPH_ID_SBC5,
+	PERIPH_ID_SBC6,
+	PERIPH_ID_AUDIO,
+	PERIPH_ID_APBIF,
+	PERIPH_ID_DAM0,
+	PERIPH_ID_DAM1,
+	PERIPH_ID_DAM2,
+	PERIPH_ID_HDA2CODEC2X,
+
+	/* 16 */
+	PERIPH_ID_ATOMICS,
+	PERIPH_ID_EX_RESERVED17,
+	PERIPH_ID_EX_RESERVED18,
+	PERIPH_ID_EX_RESERVED19,
+	PERIPH_ID_EX_RESERVED20,
+	PERIPH_ID_EX_RESERVED21,
+	PERIPH_ID_EX_RESERVED22,
+	PERIPH_ID_ACTMON,
+
+	/* 24 */
+	PERIPH_ID_EX_RESERVED24,
+	PERIPH_ID_EX_RESERVED25,
+	PERIPH_ID_EX_RESERVED26,
+	PERIPH_ID_EX_RESERVED27,
+	PERIPH_ID_SATA,
+	PERIPH_ID_HDA,
+	PERIPH_ID_EX_RESERVED30,
+	PERIPH_ID_EX_RESERVED31,
+
+	/* W word: 31:0 */
+	PERIPH_ID_HDA2HDMICODEC,
+	PERIPH_ID_SATACOLD,
+	PERIPH_ID_RESERVED0_PCIERX0,
+	PERIPH_ID_RESERVED1_PCIERX1,
+	PERIPH_ID_RESERVED2_PCIERX2,
+	PERIPH_ID_RESERVED3_PCIERX3,
+	PERIPH_ID_RESERVED4_PCIERX4,
+	PERIPH_ID_RESERVED5_PCIERX5,
+
+	/* 40 */
+	PERIPH_ID_CEC,
+	PERIPH_ID_RESERVED6_PCIE2,
+	PERIPH_ID_RESERVED7_EMC,
+	PERIPH_ID_RESERVED8_HDMI,
+	PERIPH_ID_RESERVED9_SATA,
+	PERIPH_ID_RESERVED10_MIPI,
+	PERIPH_ID_EX_RESERVED46,
+	PERIPH_ID_EX_RESERVED47,
+
+	PERIPH_ID_COUNT,
+
+};
+#endif	/* _CLOCK_TABLES_H */
diff --git a/arch/arm/include/asm/arch-tegra3/clock.h b/arch/arm/include/asm/arch-tegra3/clock.h
index c11066760e..914f721725 100644
--- a/arch/arm/include/asm/arch-tegra3/clock.h
+++ b/arch/arm/include/asm/arch-tegra3/clock.h
@@ -19,4 +19,5 @@
  * MA 02111-1307 USA
  */
 
+#include "asm/arch/clock-tables.h"
 #include "asm/arch-tegra/clock.h"