diff options
| author | Simon Glass <sjg@chromium.org> | 2011-11-29 17:20:22 -0800 |
|---|---|---|
| committer | Gerrit <chrome-bot@google.com> | 2011-12-05 11:55:05 -0800 |
| commit | 23ef5fa2a6ae8f6c76524fd441a4bcbe385533ca (patch) | |
| tree | 7bad5e0ee1a8bc910a97f04e4bcfd2b16f609ff3 /arch/arm | |
| parent | 28baa5606172c45730b507f4c6047718f7a85d6b (diff) | |
tegra: Add a clock rate parameter to clock_early_init()
Since PLLP can be set to two different values, make it a parameter
to the function that sets up the PLLs.
BUG=chromium-os:23496
TEST=build and boot on Seaboard, T33, Kaen
Change-Id: I81ccc1cc3356796793ec2dd4ab22ed7fbd52f01d
Reviewed-on: https://gerrit.chromium.org/gerrit/12245
Commit-Ready: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv7/tegra-common/clock.c | 32 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/clock.h | 9 |
2 files changed, 23 insertions, 18 deletions
diff --git a/arch/arm/cpu/armv7/tegra-common/clock.c b/arch/arm/cpu/armv7/tegra-common/clock.c index 1334df21c7..8964c66208 100644 --- a/arch/arm/cpu/armv7/tegra-common/clock.c +++ b/arch/arm/cpu/armv7/tegra-common/clock.c @@ -1348,8 +1348,9 @@ uint32_t check_is_tegra_processor_reset(void) return (base_reg & bf_mask(PLL_BASE_OVRRIDE)) ? 0 : 1; } -void clock_early_init(void) +int clock_early_init(ulong pllp_base) { + unsigned osc_freq_mhz; /* * PLLP output frequency set to 216Mh * PLLC output frequency set to 228Mhz (Tegra3) or 600MHz (Tegra2) @@ -1357,23 +1358,11 @@ void clock_early_init(void) */ switch (clock_get_osc_freq()) { case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ -#if defined(CONFIG_SYS_PLLP_BASE_IS_408MHZ) - clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8); - clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8); -#else - clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8); - clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8); -#endif + osc_freq_mhz = 12; break; case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ -#if defined(CONFIG_SYS_PLLP_BASE_IS_408MHZ) - clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8); - clock_set_rate(CLOCK_ID_CGENERAL, 456, 26, 1, 8); -#else - clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8); - clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); -#endif + osc_freq_mhz = 26; break; case CLOCK_OSC_FREQ_13_0: @@ -1384,8 +1373,19 @@ void clock_early_init(void) * message and the UART likely won't work anyway due to the * oscillator being wrong. */ - break; + return -1; } + + if (pllp_base == 408000000) { + clock_set_rate(CLOCK_ID_PERIPH, 408, osc_freq_mhz, 0, 8); + clock_set_rate(CLOCK_ID_CGENERAL, 456, osc_freq_mhz, 1, 8); + } else { + assert(pllp_base == 216000000); + clock_set_rate(CLOCK_ID_PERIPH, 432, osc_freq_mhz, 1, 8); + clock_set_rate(CLOCK_ID_CGENERAL, 600, osc_freq_mhz, 0, 8); + } + + return 0; } void clock_init(void) diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index 7cdfe935ab..83abc43158 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -238,7 +238,12 @@ int clock_verify(void); /* Initialize the clocks */ void clock_init(void); -/* Initialize the PLLs */ -void clock_early_init(void); +/** + * Initialize the PLLs + * + * @param pllp_base Base clock for PLLP - should be 408000000 or + * 216000000 are supported for the moment. + */ +int clock_early_init(ulong pllp_base); #endif |