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authorKeerthy <j-keerthy@ti.com>2016-10-29 15:19:10 +0530
committerTom Rini <trini@konsulko.com>2016-11-13 15:54:36 -0500
commit06d43c808d61580d977526deca328e33382b40c8 (patch)
tree8d11bb1963b909be69edcad3e0e5b6fee587b395 /arch/arm
parent2b373cb83cae37d2cb1af7f880c1ba739956d9b3 (diff)
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode
While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/include/asm/system.h2
-rw-r--r--arch/arm/lib/cache-cp15.c5
2 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index c3c88d2b30..574a0e775f 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -331,7 +331,7 @@ static inline void set_dacr(unsigned int val)
/* options available for data cache on each page */
enum dcache_option {
- DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0),
+ DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index e9f9fc98f7..e9bbcf5122 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -71,8 +71,13 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
start = start >> MMU_SECTION_SHIFT;
+#ifdef CONFIG_ARMV7_LPAE
+ debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
+ option);
+#else
debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
option);
+#endif
for (upto = start; upto < end; upto++)
set_section_dcache(upto, option);