MLK-23834: Move SNVS board config to headers files

Separate the different configuration of the SNVS and DGO for
the different platforms.

It allows to easily add or change the configuration for a
specific board.

In each configuration file, the following configuration are
predefined:
 - tamper connected to a ground line
 - tamper connected to a vcc line
 - tamper configured as active line

Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
(cherry picked from commit 8294483682787f0627c514ec5333c853b16ada10)
(cherry picked from commit fe44d894e488b8fda57f0c37f2fe2f2238097b71)
(cherry picked from commit d1366d208278ace4119f405d12e8bed62fbae4b2)

6 files changed, 675 insertions, 243 deletions

diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc.c b/arch/arm/mach-imx/imx8/snvs_security_sc.c
index 0c89cea6006..1e4c43cedd9 100644
--- a/arch/arm/mach-imx/imx8/snvs_security_sc.c
+++ b/arch/arm/mach-imx/imx8/snvs_security_sc.c
@@ -26,6 +26,7 @@
 #include <asm/arch-imx8/imx8-pins.h>
 #include <asm/arch-imx8/snvs_security_sc.h>
 #include <asm/global_data.h>
+#include "snvs_security_sc_conf_board.h"
 
 #define SC_WRITE_CONF 1
 
@@ -33,258 +34,17 @@
 #define SRTC_EN 0x1
 #define DP_EN BIT(5)
 
-struct snvs_security_sc_conf {
-	struct snvs_hp_conf {
-		u32 lock;		/* HPLR - HP Lock */
-		u32 __cmd;		/* HPCOMR - HP Command */
-		u32 __ctl;		/* HPCR - HP Control */
-		u32 secvio_intcfg;	/* HPSICR - Security Violation Int
-					 * Config
-					 */
-		u32 secvio_ctl;		/* HPSVCR - Security Violation Control*/
-		u32 status;		/* HPSR - HP Status */
-		u32 secvio_status;	/* HPSVSR - Security Violation Status */
-		u32 __ha_counteriv;	/* High Assurance Counter IV */
-		u32 __ha_counter;		/* High Assurance Counter */
-		u32 __rtc_msb;		/* Real Time Clock/Counter MSB */
-		u32 __rtc_lsb;		/* Real Time Counter LSB */
-		u32 __time_alarm_msb;	/* Time Alarm MSB */
-		u32 __time_alarm_lsb;	/* Time Alarm LSB */
-	} hp;
-	struct snvs_lp_conf {
-		u32 lock;
-		u32 __ctl;
-		u32 __mstr_key_ctl;	/* Master Key Control */
-		u32 secvio_ctl;		/* Security Violation Control */
-		u32 tamper_filt_cfg;	/* Tamper Glitch Filters Configuration*/
-		u32 tamper_det_cfg;	/* Tamper Detectors Configuration */
-		u32 status;
-		u32 __srtc_msb;		/* Secure Real Time Clock/Counter MSB */
-		u32 __srtc_lsb;		/* Secure Real Time Clock/Counter LSB */
-		u32 __time_alarm;		/* Time Alarm */
-		u32 __smc_msb;		/* Secure Monotonic Counter MSB */
-		u32 __smc_lsb;		/* Secure Monotonic Counter LSB */
-		u32 __pwr_glitch_det;	/* Power Glitch Detector */
-		u32 __gen_purpose;
-		u8 __zmk[32];		/* Zeroizable Master Key */
-		u32 __rsvd0;
-		u32 __gen_purposes[4];	/* gp0_30 to gp0_33 */
-		u32 tamper_det_cfg2;	/* Tamper Detectors Configuration2 */
-		u32 tamper_det_status;	/* Tamper Detectors status */
-		u32 tamper_filt1_cfg;	/* Tamper Glitch Filter1 Configuration*/
-		u32 tamper_filt2_cfg;	/* Tamper Glitch Filter2 Configuration*/
-		u32 __rsvd1[4];
-		u32 act_tamper1_cfg;	/* Active Tamper1 Configuration */
-		u32 act_tamper2_cfg;	/* Active Tamper2 Configuration */
-		u32 act_tamper3_cfg;	/* Active Tamper3 Configuration */
-		u32 act_tamper4_cfg;	/* Active Tamper4 Configuration */
-		u32 act_tamper5_cfg;	/* Active Tamper5 Configuration */
-		u32 __rsvd2[3];
-		u32 act_tamper_ctl;	/* Active Tamper Control */
-		u32 act_tamper_clk_ctl;	/* Active Tamper Clock Control */
-		u32 act_tamper_routing_ctl1;/* Active Tamper Routing Control1 */
-		u32 act_tamper_routing_ctl2;/* Active Tamper Routing Control2 */
-	} lp;
-};
-
-static struct snvs_security_sc_conf snvs_default_config = {
-	.hp = {
-		.lock = 0x1f0703ff,
-		.secvio_intcfg = 0x8000002f,
-		.secvio_ctl = 0xC000007f,
-	},
-	.lp = {
-		.lock = 0x1f0003ff,
-		.secvio_ctl = 0x36,
-		.tamper_filt_cfg = 0,
-		.tamper_det_cfg = 0x76, /* analogic tampers
-					 * + rollover tampers
-					 */
-		.tamper_det_cfg2 = 0,
-		.tamper_filt1_cfg = 0,
-		.tamper_filt2_cfg = 0,
-		.act_tamper1_cfg = 0,
-		.act_tamper2_cfg = 0,
-		.act_tamper3_cfg = 0,
-		.act_tamper4_cfg = 0,
-		.act_tamper5_cfg = 0,
-		.act_tamper_ctl = 0,
-		.act_tamper_clk_ctl = 0,
-		.act_tamper_routing_ctl1 = 0,
-		.act_tamper_routing_ctl2 = 0,
-	}
-};
-
-static struct snvs_security_sc_conf snvs_passive_vcc_config = {
-	.hp = {
-		.lock = 0x1f0703ff,
-		.secvio_intcfg = 0x8000002f,
-		.secvio_ctl = 0xC000007f,
-	},
-	.lp = {
-		.lock = 0x1f0003ff,
-		.secvio_ctl = 0x36,
-		.tamper_filt_cfg = 0,
-		.tamper_det_cfg = 0x276, /* ET1 will trig on line at GND
-					  *  + analogic tampers
-					  *  + rollover tampers
-					  */
-		.tamper_det_cfg2 = 0,
-		.tamper_filt1_cfg = 0,
-		.tamper_filt2_cfg = 0,
-		.act_tamper1_cfg = 0,
-		.act_tamper2_cfg = 0,
-		.act_tamper3_cfg = 0,
-		.act_tamper4_cfg = 0,
-		.act_tamper5_cfg = 0,
-		.act_tamper_ctl = 0,
-		.act_tamper_clk_ctl = 0,
-		.act_tamper_routing_ctl1 = 0,
-		.act_tamper_routing_ctl2 = 0,
-	}
-};
-
-static struct snvs_security_sc_conf snvs_passive_gnd_config = {
-	.hp = {
-		.lock = 0x1f0703ff,
-		.secvio_intcfg = 0x8000002f,
-		.secvio_ctl = 0xC000007f,
-	},
-	.lp = {
-		.lock = 0x1f0003ff,
-		.secvio_ctl = 0x36,
-		.tamper_filt_cfg = 0,
-		.tamper_det_cfg = 0xa76, /* ET1 will trig on line at VCC
-					  *  + analogic tampers
-					  *  + rollover tampers
-					  */
-		.tamper_det_cfg2 = 0,
-		.tamper_filt1_cfg = 0,
-		.tamper_filt2_cfg = 0,
-		.act_tamper1_cfg = 0,
-		.act_tamper2_cfg = 0,
-		.act_tamper3_cfg = 0,
-		.act_tamper4_cfg = 0,
-		.act_tamper5_cfg = 0,
-		.act_tamper_ctl = 0,
-		.act_tamper_clk_ctl = 0,
-		.act_tamper_routing_ctl1 = 0,
-		.act_tamper_routing_ctl2 = 0,
-	}
-};
-
-static struct snvs_security_sc_conf snvs_active_config = {
-	.hp = {
-		.lock = 0x1f0703ff,
-		.secvio_intcfg = 0x8000002f,
-		.secvio_ctl = 0xC000007f,
-	},
-	.lp = {
-		.lock = 0x1f0003ff,
-		.secvio_ctl = 0x36,
-		.tamper_filt_cfg = 0x00800000, /* Enable filtering */
-		.tamper_det_cfg = 0x276, /* ET1 enabled + analogic tampers
-					  *  + rollover tampers
-					  */
-		.tamper_det_cfg2 = 0,
-		.tamper_filt1_cfg = 0,
-		.tamper_filt2_cfg = 0,
-		.act_tamper1_cfg = 0x84001111,
-		.act_tamper2_cfg = 0,
-		.act_tamper3_cfg = 0,
-		.act_tamper4_cfg = 0,
-		.act_tamper5_cfg = 0,
-		.act_tamper_ctl = 0x00010001,
-		.act_tamper_clk_ctl = 0,
-		.act_tamper_routing_ctl1 = 0x1,
-		.act_tamper_routing_ctl2 = 0,
-	}
-};
-
+#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO
 static struct snvs_security_sc_conf *get_snvs_config(void)
 {
 	return &snvs_default_config;
 }
 
-struct snvs_dgo_conf {
-	u32 tamper_offset_ctl;
-	u32 tamper_pull_ctl;
-	u32 tamper_ana_test_ctl;
-	u32 tamper_sensor_trim_ctl;
-	u32 tamper_misc_ctl;
-	u32 tamper_core_volt_mon_ctl;
-};
-
-static struct snvs_dgo_conf snvs_dgo_default_config = {
-	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
-};
-
-static struct snvs_dgo_conf snvs_dgo_passive_vcc_config = {
-	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
-	.tamper_pull_ctl = 0x00000001, /* Pull down ET1 */
-#ifdef CONFIG_TARGET_IMX8QXP_MEK
-	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
-#endif /* CONFIG_TARGET_IMX8QXP_MEK */
-};
-
-static struct snvs_dgo_conf snvs_dgo_passive_gnd_config = {
-	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
-	.tamper_pull_ctl = 0x00000401, /* Pull up ET1 */
-#ifdef CONFIG_TARGET_IMX8QXP_MEK
-	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
-#endif /* CONFIG_TARGET_IMX8QXP_MEK */
-};
-
-static struct snvs_dgo_conf snvs_dgo_active_config = {
-	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
-#ifdef CONFIG_TARGET_IMX8QXP_MEK
-	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
-#endif /* CONFIG_TARGET_IMX8QXP_MEK */
-};
-
 static struct snvs_dgo_conf *get_snvs_dgo_config(void)
 {
 	return &snvs_dgo_default_config;
 }
-
-struct tamper_pin_cfg {
-	u32 pad;
-	u32 mux_conf;
-};
-
-static struct tamper_pin_cfg tamper_pin_list_default_config[] = {
-#ifdef CONFIG_TARGET_IMX8QXP_MEK
-	{SC_P_CSI_D00, 0}, /* Tamp_Out0 */
-	{SC_P_CSI_D01, 0}, /* Tamp_Out1 */
-	{SC_P_CSI_D02, 0}, /* Tamp_Out2 */
-	{SC_P_CSI_D03, 0}, /* Tamp_Out3 */
-	{SC_P_CSI_D04, 0}, /* Tamp_Out4 */
-	{SC_P_CSI_D05, 0}, /* Tamp_In0 */
-	{SC_P_CSI_D06, 0}, /* Tamp_In1 */
-	{SC_P_CSI_D07, 0}, /* Tamp_In2 */
-	{SC_P_CSI_HSYNC, 0}, /* Tamp_In3 */
-	{SC_P_CSI_VSYNC, 0}, /* Tamp_In4 */
-#endif /* CONFIG_TARGET_IMX8QXP_MEK */
-};
-
-static struct tamper_pin_cfg tamper_pin_list_passive_vcc_config[] = {
-#ifdef CONFIG_TARGET_IMX8QXP_MEK
-	{SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
-#endif /* CONFIG_TARGET_IMX8QXP_MEK */
-};
-
-static struct tamper_pin_cfg tamper_pin_list_passive_gnd_config[] = {
-#ifdef CONFIG_TARGET_IMX8QXP_MEK
-	{SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
-#endif /* CONFIG_TARGET_IMX8QXP_MEK */
-};
-
-static struct tamper_pin_cfg tamper_pin_list_active_config[] = {
-#ifdef CONFIG_TARGET_IMX8QXP_MEK
-	{SC_P_CSI_D00, 0x1a000060}, /* Tamp_Out0 */ /* Sel tamper + OD */
-	{SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
-#endif /* CONFIG_TARGET_IMX8QXP_MEK */
-};
+#endif
 
 #define TAMPER_PIN_LIST_CHOSEN tamper_pin_list_default_config
 
diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc_conf.h b/arch/arm/mach-imx/imx8/snvs_security_sc_conf.h
new file mode 100644
index 00000000000..79c5ed57c3a
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/snvs_security_sc_conf.h
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP.
+ */
+
+#ifndef SNVS_SECURITY_SC_CONF_H_
+#define SNVS_SECURITY_SC_CONF_H_
+
+/*
+ * File to list different example of tamper configuration:
+ * - default
+ * - passive to ground
+ * - passive to vcc
+ * - active
+ *
+ * for the different platform supported:
+ * - imx8qxp-mek
+ * - imx8qm-mek
+ * - imx8dxl-evk
+ */
+
+#include <asm/arch-imx8/imx8-pins.h>
+
+/* Definition of the structures */
+
+struct snvs_security_sc_conf {
+	struct snvs_hp_conf {
+		u32 lock;		/* HPLR - HP Lock */
+		u32 __cmd;		/* HPCOMR - HP Command */
+		u32 __ctl;		/* HPCR - HP Control */
+		u32 secvio_intcfg;	/* HPSICR - Security Violation Int
+					 * Config
+					 */
+		u32 secvio_ctl;		/* HPSVCR - Security Violation Control*/
+		u32 status;		/* HPSR - HP Status */
+		u32 secvio_status;	/* HPSVSR - Security Violation Status */
+		u32 __ha_counteriv;	/* High Assurance Counter IV */
+		u32 __ha_counter;		/* High Assurance Counter */
+		u32 __rtc_msb;		/* Real Time Clock/Counter MSB */
+		u32 __rtc_lsb;		/* Real Time Counter LSB */
+		u32 __time_alarm_msb;	/* Time Alarm MSB */
+		u32 __time_alarm_lsb;	/* Time Alarm LSB */
+	} hp;
+	struct snvs_lp_conf {
+		u32 lock;
+		u32 __ctl;
+		u32 __mstr_key_ctl;	/* Master Key Control */
+		u32 secvio_ctl;		/* Security Violation Control */
+		u32 tamper_filt_cfg;	/* Tamper Glitch Filters Configuration*/
+		u32 tamper_det_cfg;	/* Tamper Detectors Configuration */
+		u32 status;
+		u32 __srtc_msb;		/* Secure Real Time Clock/Counter MSB */
+		u32 __srtc_lsb;		/* Secure Real Time Clock/Counter LSB */
+		u32 __time_alarm;		/* Time Alarm */
+		u32 __smc_msb;		/* Secure Monotonic Counter MSB */
+		u32 __smc_lsb;		/* Secure Monotonic Counter LSB */
+		u32 __pwr_glitch_det;	/* Power Glitch Detector */
+		u32 __gen_purpose;
+		u8 __zmk[32];		/* Zeroizable Master Key */
+		u32 __rsvd0;
+		u32 __gen_purposes[4];	/* gp0_30 to gp0_33 */
+		u32 tamper_det_cfg2;	/* Tamper Detectors Configuration2 */
+		u32 tamper_det_status;	/* Tamper Detectors status */
+		u32 tamper_filt1_cfg;	/* Tamper Glitch Filter1 Configuration*/
+		u32 tamper_filt2_cfg;	/* Tamper Glitch Filter2 Configuration*/
+		u32 __rsvd1[4];
+		u32 act_tamper1_cfg;	/* Active Tamper1 Configuration */
+		u32 act_tamper2_cfg;	/* Active Tamper2 Configuration */
+		u32 act_tamper3_cfg;	/* Active Tamper3 Configuration */
+		u32 act_tamper4_cfg;	/* Active Tamper4 Configuration */
+		u32 act_tamper5_cfg;	/* Active Tamper5 Configuration */
+		u32 __rsvd2[3];
+		u32 act_tamper_ctl;	/* Active Tamper Control */
+		u32 act_tamper_clk_ctl;	/* Active Tamper Clock Control */
+		u32 act_tamper_routing_ctl1;/* Active Tamper Routing Control1 */
+		u32 act_tamper_routing_ctl2;/* Active Tamper Routing Control2 */
+	} lp;
+};
+
+struct snvs_dgo_conf {
+	u32 tamper_offset_ctl;
+	u32 tamper_pull_ctl;
+	u32 tamper_ana_test_ctl;
+	u32 tamper_sensor_trim_ctl;
+	u32 tamper_misc_ctl;
+	u32 tamper_core_volt_mon_ctl;
+};
+
+struct tamper_pin_cfg {
+	u32 pad;
+	u32 mux_conf;
+};
+
+#define TAMPER_NOT_DEFINED -1
+#define TAMPER_NO_IOMUX TAMPER_NOT_DEFINED
+
+/* There is 10 tampers and the list start at 1 */
+enum EXT_TAMPER {
+	EXT_TAMPER_ET1 = 0,
+	EXT_TAMPER_ET2 = 1,
+	EXT_TAMPER_ET3 = 2,
+	EXT_TAMPER_ET4 = 3,
+	EXT_TAMPER_ET5 = 4,
+	EXT_TAMPER_ET6 = 5,
+	EXT_TAMPER_ET7 = 6,
+	EXT_TAMPER_ET8 = 7,
+	EXT_TAMPER_ET9 = 8,
+	EXT_TAMPER_ET10 = 9,
+};
+
+enum ACT_TAMPER {
+	ACT_TAMPER_AT1 = EXT_TAMPER_ET6,
+	ACT_TAMPER_AT2 = EXT_TAMPER_ET7,
+	ACT_TAMPER_AT3 = EXT_TAMPER_ET8,
+	ACT_TAMPER_AT4 = EXT_TAMPER_ET9,
+	ACT_TAMPER_AT5 = EXT_TAMPER_ET10,
+};
+
+#endif /* SNVS_SECURITY_SC_CONF_H_ */
diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8dxl_evk.h b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8dxl_evk.h
new file mode 100644
index 00000000000..2b4e6bc27f4
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8dxl_evk.h
@@ -0,0 +1,168 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP.
+ */
+
+#ifndef SNVS_SECURITY_SC_CONF_8DXL_EVK_H_
+#define SNVS_SECURITY_SC_CONF_8DXL_EVK_H_
+
+#include "snvs_security_sc_conf.h"
+
+static __maybe_unused struct snvs_security_sc_conf snvs_default_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x76, /* analogic tampers
+					 * + rollover tampers
+					 */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_default_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+};
+
+static __maybe_unused struct snvs_security_sc_conf snvs_passive_vcc_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x076, /* analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0x11, /* ET3 + ET7 will trig on line at GND*/
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_security_sc_conf snvs_passive_gnd_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x076, /* analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0x110011, /* ET3 + ET7 will trig on line at
+					      * VCC
+					      */
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_security_sc_conf snvs_active_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x076, /* analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0x10, /* Enable ET7 tamper */
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0x80, /* Enable filtering */
+		.act_tamper1_cfg = 0x84001111,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0x10001,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0x1000000, /* Route AT1 to ET 7 */
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_vcc_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_pull_ctl = 0x00000044, /* Pull down IN4 and OUT0 */
+	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_gnd_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_pull_ctl = 0x00011044, /* Pull down IN4 and OUT0 */
+	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_active_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
+};
+
+static struct tamper_pin_cfg tamper_pin_list_default_config[] = {
+	{SC_P_SNVS_TAMPER_IN0, 0}, /* Tamp_In0 */
+	{SC_P_SNVS_TAMPER_IN1, 0}, /* Tamp_In1 */
+	{SC_P_SNVS_TAMPER_IN2, 0}, /* Tamp_In2 */
+	{SC_P_SNVS_TAMPER_IN3, 0}, /* Tamp_In3 */
+	{TAMPER_NO_IOMUX, 0}, /* Tamp_In4 */
+	{TAMPER_NO_IOMUX, 0}, /* Tamp_Out0 */
+	{SC_P_SNVS_TAMPER_OUT1, 0}, /* Tamp_Out1 */
+	{SC_P_SNVS_TAMPER_OUT2, 0}, /* Tamp_Out2 */
+	{SC_P_SNVS_TAMPER_OUT3, 0}, /* Tamp_Out3 */
+	{SC_P_SNVS_TAMPER_OUT4, 0}, /* Tamp_Out4 */
+};
+
+static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_vcc_config[] = {
+};
+
+static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_gnd_config[] = {
+};
+
+static __maybe_unused struct tamper_pin_cfg tamper_pin_list_active_config[] = {
+};
+
+#endif /* SNVS_SECURITY_SC_CONF_8DXL_EVK_H_ */
diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qm_mek.h b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qm_mek.h
new file mode 100644
index 00000000000..20dad8b126b
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qm_mek.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP.
+ */
+
+#ifndef SNVS_SECURITY_SC_CONF_8QM_MEK_H_
+#define SNVS_SECURITY_SC_CONF_8QM_MEK_H_
+
+#include "snvs_security_sc_conf.h"
+
+/* Configuration */
+
+static __maybe_unused struct snvs_security_sc_conf snvs_default_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x76, /* analogic tampers
+					 * + rollover tampers
+					 */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_default_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+};
+
+static __maybe_unused struct snvs_security_sc_conf snvs_passive_vcc_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x276, /* ET1 will trig on line at GND
+					  *  + analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_security_sc_conf snvs_passive_gnd_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0xa76, /* ET1 will trig on line at VCC
+					  *  + analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_security_sc_conf snvs_active_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0x00800000, /* Enable filtering */
+		.tamper_det_cfg = 0x276, /* ET1 enabled + analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0x84001111,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0x00010001,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0x1,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_vcc_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_pull_ctl = 0x00000001, /* Pull down ET1 */
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_gnd_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_pull_ctl = 0x00000401, /* Pull up ET1 */
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_active_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+};
+
+static struct tamper_pin_cfg tamper_pin_list_default_config[] = {
+};
+
+static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_vcc_config[] = {
+};
+
+static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_gnd_config[] = {
+};
+
+static __maybe_unused struct tamper_pin_cfg tamper_pin_list_active_config[] = {
+};
+
+#endif /* SNVS_SECURITY_SC_CONF_8QM_MEK_H_ */
diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qxp_mek.h b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qxp_mek.h
new file mode 100644
index 00000000000..2cd3461008d
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qxp_mek.h
@@ -0,0 +1,172 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP.
+ */
+
+#ifndef SNVS_SECURITY_SC_CONF_8QXP_MEK_H_
+#define SNVS_SECURITY_SC_CONF_8QXP_MEK_H_
+
+#include "snvs_security_sc_conf.h"
+
+static __maybe_unused struct snvs_security_sc_conf snvs_default_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x76, /* analogic tampers
+					 * + rollover tampers
+					 */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_default_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+};
+
+static __maybe_unused struct snvs_security_sc_conf snvs_passive_vcc_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x276, /* ET1 will trig on line at GND
+					  *  + analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_security_sc_conf snvs_passive_gnd_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0xa76, /* ET1 will trig on line at VCC
+					  *  + analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_security_sc_conf snvs_active_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0x00800000, /* Enable filtering */
+		.tamper_det_cfg = 0x276, /* ET1 enabled + analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0x84001111,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0x00010001,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0x1,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_vcc_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_pull_ctl = 0x00000001, /* Pull down ET1 */
+	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_gnd_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_pull_ctl = 0x00000401, /* Pull up ET1 */
+	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_active_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
+};
+
+static struct tamper_pin_cfg tamper_pin_list_default_config[] = {
+	{SC_P_CSI_D05, 0}, /* Tamp_In0 */
+	{SC_P_CSI_D06, 0}, /* Tamp_In1 */
+	{SC_P_CSI_D07, 0}, /* Tamp_In2 */
+	{SC_P_CSI_HSYNC, 0}, /* Tamp_In3 */
+	{SC_P_CSI_VSYNC, 0}, /* Tamp_In4 */
+	{SC_P_CSI_D00, 0}, /* Tamp_Out0 */
+	{SC_P_CSI_D01, 0}, /* Tamp_Out1 */
+	{SC_P_CSI_D02, 0}, /* Tamp_Out2 */
+	{SC_P_CSI_D03, 0}, /* Tamp_Out3 */
+	{SC_P_CSI_D04, 0}, /* Tamp_Out4 */
+};
+
+static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_vcc_config[] = {
+	{SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
+};
+
+static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_gnd_config[] = {
+	{SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
+};
+
+static __maybe_unused struct tamper_pin_cfg tamper_pin_list_active_config[] = {
+	{SC_P_CSI_D00, 0x1a000060}, /* Tamp_Out0 */ /* Sel tamper + OD */
+	{SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
+};
+
+#endif /* SNVS_SECURITY_SC_CONF_8QXP_MEK_H_ */
diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc_conf_board.h b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_board.h
new file mode 100644
index 00000000000..250952b7df6
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_board.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP.
+ */
+
+#ifndef SNVS_SECURITY_SC_CONF_BOARD_H_
+#define SNVS_SECURITY_SC_CONF_BOARD_H_
+
+#ifdef CONFIG_TARGET_IMX8QM_MEK
+#include "snvs_security_sc_conf_8qm_mek.h"
+#elif CONFIG_TARGET_IMX8QXP_MEK
+#include "snvs_security_sc_conf_8qxp_mek.h"
+#elif CONFIG_TARGET_IMX8DXL_EVK
+#include "snvs_security_sc_conf_8dxl_evk.h"
+#else
+
+#include "snvs_security_sc_conf.h"
+
+/* Default configuration of the tamper for all boards */
+static __maybe_unused struct snvs_security_sc_conf snvs_default_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x76, /* analogic tampers
+					 * + rollover tampers
+					 */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_default_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+};
+
+static struct tamper_pin_cfg tamper_pin_list_default_config[] = {0};
+
+#endif
+
+#endif /* SNVS_SECURITY_SC_CONF_BOARD_H_ */