diff options
| author | Ji Luo <ji.luo@nxp.com> | 2022-04-18 16:33:13 +0800 |
|---|---|---|
| committer | Ji Luo <ji.luo@nxp.com> | 2022-04-20 09:49:54 +0800 |
| commit | 8eac078fc59571dacb0f2d9623bf8384288a157b (patch) | |
| tree | 4d36369766a198b4f1d19ff4bfcec741ebb5f899 /arch/arm | |
| parent | 6a5796048bc330f99f41ae6ae67445ad55e1cf07 (diff) | |
MA-19038 Android: Add imx8/imx8m/imx8ulp reference boards support
Add configs to support imx8/imx8m/imx8ulp reference boards, each platform
has specific header files include.
Test: sanity test on imx8/imx8m/imx8ulp platforms.
Change-Id: I05708fbc108a78ac9b3415cb782bf1013e2f7012
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/dts/imx8mm-evk.dts | 4 | ||||
| -rw-r--r-- | arch/arm/dts/imx8mn-evk.dts | 5 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-imx8/imx-regs.h | 1 |
3 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/dts/imx8mm-evk.dts b/arch/arm/dts/imx8mm-evk.dts index 19f30d22ba..c07eb8be8e 100644 --- a/arch/arm/dts/imx8mm-evk.dts +++ b/arch/arm/dts/imx8mm-evk.dts @@ -12,6 +12,10 @@ model = "NXP i.MX8MM EVK board"; compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + }; + aliases { spi0 = &flexspi; }; diff --git a/arch/arm/dts/imx8mn-evk.dts b/arch/arm/dts/imx8mn-evk.dts index cd11fb28f5..4d1c350f86 100644 --- a/arch/arm/dts/imx8mn-evk.dts +++ b/arch/arm/dts/imx8mn-evk.dts @@ -12,6 +12,11 @@ / { model = "NXP i.MX8MNano EVK board"; compatible = "fsl,imx8mn-evk", "fsl,imx8mn"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + }; + }; &A53_0 { diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h index 63d99c21d1..b55bdcfe45 100644 --- a/arch/arm/include/asm/arch-imx8/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8/imx-regs.h @@ -57,6 +57,7 @@ #define USB_PHY0_BASE_ADDR 0x5b100000 #define USB_PHY1_BASE_ADDR 0x5b110000 +#define CAAM_ARB_BASE_ADDR (0x31800000) #define CONFIG_SYS_FSL_SEC_ADDR (0x31400000) #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 |