diff options
author | Tom Rini <trini@konsulko.com> | 2022-05-23 09:25:39 -0400 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2022-05-23 09:25:39 -0400 |
commit | 004d30c786056d443d40428c4b1c11e2f8f0bc32 (patch) | |
tree | a6c7d28590d20c5f88f292804bcb22ebfa36d942 /arch/arm | |
parent | 6f00b97d7e5760d92566317dde6c4b9224790827 (diff) | |
parent | 4d573d5c98234cad328de77c773c3c3d79258255 (diff) |
Merge tag 'u-boot-imx-20220523' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20220523
-------------------
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/12087
Additionally to u-boot-imx20200520:
- DH MX8MP
- i.MX GPIO: reading GPIO when direction is output
- Menlo i.MX53: switch to DM
And from u-boot-imx20200520:
- fix Verdin hang
- add pca9450 regulator
- conversion to DM_SERIAL
- NAND block handling
- fix crypto
- enable cache on some boards
- add ACC board (MX6)
Diffstat (limited to 'arch/arm')
50 files changed, 2711 insertions, 108 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 9fe1cd90487..0b3e3b20641 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -409,7 +409,7 @@ int arch_misc_init(void) ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); if (ret) - printf("Failed to initialize %s: %d\n", dev->name, ret); + printf("Failed to initialize caam_jr: %d\n", ret); } return 0; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index a71ee636afe..253008a9c13 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1648,7 +1648,7 @@ int arch_misc_init(void) ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); if (ret) - printf("Failed to initialize %s: %d\n", dev->name, ret); + printf("Failed to initialize caam_jr: %d\n", ret); } serdes_misc_init(); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 83630af4f67..3ca980aae08 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -738,6 +738,7 @@ dtb-y += \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ imx6dl-dhcom-pdk2.dtb \ + imx6dl-dhcom-picoitx.dts \ imx6dl-gw51xx.dtb \ imx6dl-gw52xx.dtb \ imx6dl-gw53xx.dtb \ @@ -771,12 +772,14 @@ dtb-y += \ imx6dl-sabreauto.dtb \ imx6dl-sabresd.dtb \ imx6dl-wandboard-revd1.dtb \ + imx6s-dhcom-drc02.dtb endif ifneq ($(CONFIG_MX6Q)$(CONFIG_MX6QDL),) dtb-y += \ imx6-apalis.dtb \ + imx6q-bosch-acc.dtb \ imx6q-cm-fx6.dtb \ imx6q-cubox-i.dtb \ imx6q-cubox-i-emmc-som-v15.dtb \ @@ -936,6 +939,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mn-beacon-kit.dtb \ imx8mq-mnt-reform2.dtb \ imx8mq-phanbell.dtb \ + imx8mp-dhcom-pdk2.dtb \ imx8mp-evk.dtb \ imx8mp-phyboard-pollux-rdk.dtb \ imx8mp-venice.dtb \ diff --git a/arch/arm/dts/imx6dl-dhcom-picoitx-u-boot.dtsi b/arch/arm/dts/imx6dl-dhcom-picoitx-u-boot.dtsi new file mode 100644 index 00000000000..16669b25333 --- /dev/null +++ b/arch/arm/dts/imx6dl-dhcom-picoitx-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+) +/* + * Copyright (C) 2022 Philip Oberfichtner <pro@denx.de> + */ + +#include "imx6qdl-dhcom-u-boot.dtsi" + +&fec { + phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/imx6dl-dhcom-picoitx.dts b/arch/arm/dts/imx6dl-dhcom-picoitx.dts new file mode 100644 index 00000000000..038bb002555 --- /dev/null +++ b/arch/arm/dts/imx6dl-dhcom-picoitx.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 DH electronics GmbH + * + * DHCOM iMX6 variant: + * DHCM-iMX6DL-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2 + * DHCOM PCB number: 493-300 or newer + * PicoITX PCB number: 487-600 or newer + */ +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-dhcom-som.dtsi" +#include "imx6qdl-dhcom-picoitx.dtsi" + +/ { + model = "DH electronics i.MX6DL DHCOM on PicoITX"; + compatible = "dh,imx6dl-dhcom-picoitx", "dh,imx6dl-dhcom-som", + "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi b/arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi new file mode 100644 index 00000000000..37c182d3185 --- /dev/null +++ b/arch/arm/dts/imx6q-bosch-acc-u-boot.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* Copyright (C) 2022 Denx Software Engineering GmbH + * Philip Oberfichtner <pro@denx.de> + */ + +/ { + chosen { + stdout-path = &uart2; + }; + + soc { + u-boot,dm-spl; + + bus@2000000 { + u-boot,dm-spl; + + spba-bus@2000000 { + u-boot,dm-spl; + }; + }; + + bus@2100000 { + u-boot,dm-spl; + }; + }; + + bootcount { + compatible = "u-boot,bootcount-pmic"; + pmic = <&pmic>; + }; +}; + +&uart1 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; + +&usdhc4 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&gpio6 { + u-boot,dm-spl; +}; + +&gpio7 { + u-boot,dm-spl; +}; + +&wdog1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx6q-bosch-acc.dts b/arch/arm/dts/imx6q-bosch-acc.dts new file mode 100644 index 00000000000..1bd4ef2fe4e --- /dev/null +++ b/arch/arm/dts/imx6q-bosch-acc.dts @@ -0,0 +1,769 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for the i.MX6-based Bosch ACC board. + * + * Copyright (C) 2016 Garz & Fricke GmbH + * Copyright (C) 2018 DENX Software Engineering GmbH, Heiko Schocher <hs@denx.de> + * Copyright (C) 2018 DENX Software Engineering GmbH, Niel Fourie <lusus@denx.de> + * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker <matthias.winker@bosch.com> + * Copyright (C) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include "imx6q.dtsi" + +/ { + model = "Bosch ACC"; + compatible = "bosch,imx6q-acc", "fsl,imx6q"; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &usdhc4; + mmc1 = &usdhc2; + serial0 = &uart2; + serial1 = &uart1; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 200000>; + brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>; + num-interpolated-steps = <10>; + default-brightness-level = <60>; + power-supply = <®_lcd>; + }; + + panel { + compatible = "dataimage,fg1001l0dsswmg01"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + refclk: refclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "12mhz_refclk"; + assigned-clocks = <&clks IMX6QDL_CLK_CKO>, + <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_CKO2_PODF>, + <&clks IMX6QDL_CLK_OSC>; + assigned-clock-rates = <0>, <12000000>, <0>; + }; + + cpus { + cpu0: cpu@0 { + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1225000 + 852000 1225000 + 792000 1150000 + 396000 950000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1225000 + 996000 1175000 + 852000 1175000 + 792000 1150000 + 396000 1150000 + >; + }; + + cpu1: cpu@1 { + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1225000 + 852000 1225000 + 792000 1150000 + 396000 950000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1225000 + 996000 1175000 + 852000 1175000 + 792000 1150000 + 396000 1150000 + >; + }; + }; + + pwm-leds { + compatible = "pwm-leds"; + + led_red: led-0 { + color = <LED_COLOR_ID_RED>; + max-brightness = <248>; + default-state = "off"; + pwms = <&pwm2 0 500000>; + }; + + led_white: led-1 { + color = <LED_COLOR_ID_WHITE>; + max-brightness = <248>; + default-state = "off"; + pwms = <&pwm3 0 500000>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_gpio_led>; + + led-2 { + color = <LED_COLOR_ID_RED>; + gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + reg_5p0: regulator-5p0 { + compatible = "regulator-fixed"; + regulator-name = "5p0"; + }; + + reg_vin: regulator-vin { + compatible = "regulator-fixed"; + regulator-name = "VIN"; + regulator-min-microvolt = <4500000>; + regulator-max-microvolt = <4500000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_usb_h2_vbus: regulator-usb-h2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5p0> ; + regulator-always-on; + }; + + reg_vsnvs: regulator-vsnvs { + compatible = "regulator-fixed"; + regulator-name = "VSNVS_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_lcd: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "LCD0 POWER"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_enable>; + gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + reg_dac: regulator-dac { + compatible = "regulator-fixed"; + regulator-name = "vref_dac"; + regulator-min-microvolt = <20000>; + regulator-max-microvolt = <20000>; + vin-supply = <®_5p0> ; + regulator-boot-on; + }; + + reg_sw4: regulator-sw4 { + compatible = "regulator-fixed"; + regulator-name = "SW4_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_sys: regulator-sys { + compatible = "regulator-fixed"; + regulator-name = "SYS_4V2"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; +}; + +®_arm { + vin-supply = <&sw2_reg>; +}; + +®_soc { + vin-supply = <&sw1c_reg>; +}; + +®_vdd1p1 { + vin-supply = <®_vsnvs>; +}; + +®_vdd2p5 { + vin-supply = <®_vsnvs>; +}; + +®_vdd3p0 { + vin-supply = <®_vsnvs>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", "enet_out"; + phy-mode = "rmii"; + phy-supply = <®_sw4>; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + smsc,disable-energy-detect; + }; + }; +}; + +&gpu_vg { + status = "disabled"; +}; + +&gpu_2d { + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1c_reg: sw1c { + regulator-name = "VDD_SOC (sw1abc)"; + regulator-min-microvolt = <1275000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-name = "VDD_ARM (sw2)"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + compatible = "regulator-fixed"; + regulator-name = "DDR_1V5a"; + regulator-boot-on; + regulator-always-on; + + }; + + sw3b_reg: sw3b { + compatible = "regulator-fixed"; + regulator-name = "DDR_1V5b"; + regulator-boot-on; + regulator-always-on; + + }; + + sw4_reg: sw4 { + regulator-name = "AUX 3V15 (sw4)"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + lm75: sensor@49 { + compatible = "national,lm75b"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lm75>; + reg = <0x49>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc: rtc@51 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + eeprom_ext: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; + + usb3503: usb@8 { + compatible = "smsc,usb3503"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3503>; + reg = <0x08>; + connect-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* Old: 0, SS: HIGH */ + intn-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; /* Old: 1, SS: HIGH */ + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* Old: 0, SS: HIGH */ + initial-mode = <1>; + clocks = <&refclk>; + clock-names = "refclk"; + refclk-frequency = <12000000>; + }; + + exc3000: touchscreen@2a { + compatible = "eeti,exc3000"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctouch>; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; + }; + + vcnl4035: light-sensor@60 { + compatible = "vishay,vcnl4035"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_proximity>; + reg = <0x60>; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + rts-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh2_idle>; + pinctrl-1 = <&pinctrl_usbh2_active>; + vbus-supply = <®_usb_h2_vbus>; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + vbus-supply = <®_usb_otg_vbus>; + disable-over-current; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + voltage-ranges = <3300 3300>; + vmmc-supply = <®_sw4>; + fsl,wp-controller; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + voltage-ranges = <3300 3300>; + vmmc-supply = <®_sw4>; + fsl,wp-controller; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; + timeout-sec=<10>; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 /* FEC INT */ + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_reset_gpio_led: reset-gpio-led-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b810 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b810 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_lcd_enable: lcdenablegrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* lcd enable */ + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /* sel6_8 */ + >; + }; + + pinctrl_lm75: lm75grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; + + pinctrl_proximity: proximitygrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x0001b0b0 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x0001b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x0001b0b0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0001b0b0 + >; + }; + + pinctrl_rtc: rtc-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 /* RTC INT */ + >; + }; + + pinctrl_ctouch: ctouch-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* CTOUCH_INT */ + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x0001b0b0 /* CTOUCH_RESET */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0001b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh2_idle: usbh2-idle-grp { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018 + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00013018 + >; + }; + + pinctrl_usbh2_active: usbh2-active-grp { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018 + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00017018 + >; + }; + + pinctrl_usb3503: usb3503-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x00000018 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* USB INT */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0001b0b0 /* USB Reset */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 /* USB Connect */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017069 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00010038 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017069 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017069 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017069 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017069 + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x0001b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x00017059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x00010059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x00017059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x00017059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x00017059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x00017059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x00017059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x00017059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x00017059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x00017059 + >; + }; + + pinctrl_wdog1: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-dhcom-drc02.dtsi b/arch/arm/dts/imx6qdl-dhcom-drc02.dtsi new file mode 100644 index 00000000000..702cd4a1b2e --- /dev/null +++ b/arch/arm/dts/imx6qdl-dhcom-drc02.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 DH electronics GmbH + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* + * Special SoM hardware required which uses the pins from micro SD card. The + * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 + * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD + * card must be disabled and the uart1 rts/cts must be output on other DHCOM + * pins, see uart1 and usdhc3 node below. + */ +&can2 { + status = "okay"; +}; + +&gpio1 { + /* + * NOTE: On DRC02, the RS485_RX_En is controlled by a separate + * GPIO line, however the i.MX6 UART driver assumes RX happens + * during TX anyway and that it only controls drive enable DE + * line. Hence, the RX is always enabled here. + */ + rs485-rx-en-hog { + gpio-hog; + gpios = <18 0>; /* GPIO Q */ + line-name = "rs485-rx-en"; + output-low; + }; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "DRC02-In1", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "DHCOM-E", "DRC02-In2", "DHCOM-H", + "DHCOM-I", "DRC02-HW0", "", "", "", "", "", "", + "", "", "", "", "DRC02-Out1", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio6 { + gpio-line-names = + "", "", "", "DRC02-Out2", "", "", "SOM-HW1", "", + "", "", "", "", "", "", "DRC02-HW2", "DRC02-HW1", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&uart1 { + /* + * Due to the use of can2 the signals for can2 Tx and Rx are routed to + * DHCOM UART1 rts/cts pins. Therefore this UART have to use DHCOM GPIOs + * for rts/cts. So configure DHCOM GPIO I as rts and GPIO M as cts. + */ + /delete-property/ uart-has-rtscts; + cts-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; /* GPIO M */ + pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>; + pinctrl-names = "default"; + rts-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ +}; + +&uart5 { + /* + * On DRC02 this UART is used as RS485 interface and RS485_TX_En is + * controlled by DHCOM GPIO P. So remove rts/cts pins and the property + * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via + * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1 + * node above. + */ + /delete-property/ uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + pinctrl-0 = <&pinctrl_uart5_core &pinctrl_dhcom_p &pinctrl_dhcom_q>; + pinctrl-names = "default"; + rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */ +}; + +&usbh1 { + disable-over-current; +}; + +&usdhc2 { /* SD card */ + status = "okay"; +}; + +&usdhc3 { + /* + * Due to the use of can2 the micro SD card on module have to be + * disabled, because the pins SD3_DAT0 and SD3_DAT1 are muxed as + * can2 Tx and Rx. + */ + status = "disabled"; +}; + +&iomuxc { + pinctrl-0 = < + /* + * The following DHCOM GPIOs are used on this board. + * Therefore, they have been removed from the list below. + * I: uart1 rts + * M: uart1 cts + * P: uart5 rs485-tx-en + * Q: uart5 rs485-rx-en + */ + &pinctrl_hog_base + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f + &pinctrl_dhcom_g &pinctrl_dhcom_h + &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l + &pinctrl_dhcom_n &pinctrl_dhcom_o + &pinctrl_dhcom_r + &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u + &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int + >; + pinctrl-names = "default"; + + pinctrl_uart5_core: uart5-core-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi index a1ffb1d6fc5..0673c21e3c3 100644 --- a/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi @@ -5,19 +5,6 @@ #include "imx6qdl-dhcom-u-boot.dtsi" -/ { - fec_vio: regulator-fec { - compatible = "regulator-fixed"; - - regulator-name = "fec-vio"; - gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; -}; - &fec { phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - phy-reset-post-delay = <10>; - - phy-supply = <&fec_vio>; }; diff --git a/arch/arm/dts/imx6qdl-dhcom-picoitx.dtsi b/arch/arm/dts/imx6qdl-dhcom-picoitx.dtsi new file mode 100644 index 00000000000..4cd4cb9543c --- /dev/null +++ b/arch/arm/dts/imx6qdl-dhcom-picoitx.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 DH electronics GmbH + */ + +#include <dt-bindings/leds/common.h> + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + led { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_YELLOW>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ + pinctrl-0 = <&pinctrl_dhcom_i>; + pinctrl-names = "default"; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "", "DHCOM-A", "", "DHCOM-B", "PicoITX-In2", "", "", + "", "", "", "", "", "", "", "", + "DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "PicoITX-In1", "DHCOM-INT", "DHCOM-H", + "DHCOM-I", "PicoITX-HW2", "", "", "", "", "", "", + "", "", "", "", "PicoITX-Out1", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio6 { + gpio-line-names = + "", "", "", "PicoITX-Out2", "", "", "SOM-HW1", "", + "", "", "", "", "", "", "PicoITX-HW0", "PicoITX-HW1", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&iomuxc { + pinctrl-0 = < + /* + * The following DHCOM GPIOs are used on this board. + * Therefore, they have been removed from the list below. + * I: yellow led + */ + &pinctrl_hog_base + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f + &pinctrl_dhcom_g &pinctrl_dhcom_h + &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l + &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o + &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r + &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u + &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int + >; + pinctrl-names = "default"; +}; diff --git a/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi b/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi index 4c3b5e82d61..190567ab7ba 100644 --- a/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-dhcom-u-boot.dtsi @@ -1,8 +1,26 @@ // SPDX-License-Identifier: (GPL-2.0+) /* * Copyright (C) 2020 Harald Seiler <hws@denx.de> + * Copyright (C) 2022 Philip Oberfichtner <pro@denx.de> */ +/ { + aliases { + eeprom0 = &eeprom0; + }; +}; + +&fec { + phy-reset-duration = <1>; + phy-reset-post-delay = <10>; + phy-supply = <®_eth_vio>; +}; + +&i2c3 { + eeprom0: eeprom@50 { + }; +}; + ®_usb_otg_vbus { gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; enable-active-high; diff --git a/arch/arm/dts/imx6qdl-gw51xx.dtsi b/arch/arm/dts/imx6qdl-gw51xx.dtsi index 812acf7ab82..139ffe012dc 100644 --- a/arch/arm/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw51xx.dtsi @@ -130,7 +130,7 @@ phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; phy-reset-duration = <10>; - phy-reset-post-delay = <100>; + phy-reset-post-delay = <300>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw52xx.dtsi b/arch/arm/dts/imx6qdl-gw52xx.dtsi index 81a9ce38b9b..1b5c836ff39 100644 --- a/arch/arm/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw52xx.dtsi @@ -196,7 +196,7 @@ phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; phy-reset-duration = <10>; - phy-reset-post-delay = <100>; + phy-reset-post-delay = <300>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw53xx.dtsi b/arch/arm/dts/imx6qdl-gw53xx.dtsi index 77ac103c2d9..e5e9e0c0589 100644 --- a/arch/arm/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw53xx.dtsi @@ -190,7 +190,7 @@ phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; phy-reset-duration = <10>; - phy-reset-post-delay = <100>; + phy-reset-post-delay = <300>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw54xx.dtsi b/arch/arm/dts/imx6qdl-gw54xx.dtsi index 98c81e9c9b5..2f41f092142 100644 --- a/arch/arm/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw54xx.dtsi @@ -227,7 +227,7 @@ phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; phy-reset-duration = <10>; - phy-reset-post-delay = <100>; + phy-reset-post-delay = <300>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw560x.dtsi b/arch/arm/dts/imx6qdl-gw560x.dtsi index 1e95267c974..6586d877204 100644 --- a/arch/arm/dts/imx6qdl-gw560x.dtsi +++ b/arch/arm/dts/imx6qdl-gw560x.dtsi @@ -281,7 +281,7 @@ phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; phy-reset-duration = <10>; - phy-reset-post-delay = <100>; + phy-reset-post-delay = <300>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw5903.dtsi b/arch/arm/dts/imx6qdl-gw5903.dtsi index 6ebf6aef2f7..1df3faba416 100644 --- a/arch/arm/dts/imx6qdl-gw5903.dtsi +++ b/arch/arm/dts/imx6qdl-gw5903.dtsi @@ -225,7 +225,7 @@ phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; phy-reset-duration = <10>; - phy-reset-post-delay = <100>; + phy-reset-post-delay = <300>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw5904.dtsi b/arch/arm/dts/imx6qdl-gw5904.dtsi index 286c7a9924c..381f605cc0d 100644 --- a/arch/arm/dts/imx6qdl-gw5904.dtsi +++ b/arch/arm/dts/imx6qdl-gw5904.dtsi @@ -203,7 +203,7 @@ phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; phy-reset-duration = <10>; - phy-reset-post-delay = <100>; + phy-reset-post-delay = <300>; status = "okay"; fixed-link { diff --git a/arch/arm/dts/imx6qdl-gw5907.dtsi b/arch/arm/dts/imx6qdl-gw5907.dtsi index a36b6e7048c..68585f84d13 100644 --- a/arch/arm/dts/imx6qdl-gw5907.dtsi +++ b/arch/arm/dts/imx6qdl-gw5907.dtsi @@ -132,7 +132,7 @@ phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; phy-reset-duration = <10>; - phy-reset-post-delay = <100>; + phy-reset-post-delay = <300>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw5910.dtsi b/arch/arm/dts/imx6qdl-gw5910.dtsi index 446c1043a76..594468dcba8 100644 --- a/arch/arm/dts/imx6qdl-gw5910.dtsi +++ b/arch/arm/dts/imx6qdl-gw5910.dtsi @@ -148,7 +148,7 @@ phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; phy-reset-duration = <10>; - phy-reset-post-delay = <100>; + phy-reset-post-delay = <300>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw5912.dtsi b/arch/arm/dts/imx6qdl-gw5912.dtsi index 8fd8fdb5147..f51ec3d62ce 100644 --- a/arch/arm/dts/imx6qdl-gw5912.dtsi +++ b/arch/arm/dts/imx6qdl-gw5912.dtsi @@ -144,7 +144,7 @@ phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; phy-reset-duration = <10>; - phy-reset-post-delay = <100>; + phy-reset-post-delay = <300>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw5913.dtsi b/arch/arm/dts/imx6qdl-gw5913.dtsi index c2c1c2b160d..44d347f04eb 100644 --- a/arch/arm/dts/imx6qdl-gw5913.dtsi +++ b/arch/arm/dts/imx6qdl-gw5913.dtsi @@ -123,7 +123,7 @@ phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; phy-reset-duration = <10>; - phy-reset-post-delay = <100>; + phy-reset-post-delay = <300>; status = "okay"; }; diff --git a/arch/arm/dts/imx6s-dhcom-drc02-u-boot.dtsi b/arch/arm/dts/imx6s-dhcom-drc02-u-boot.dtsi new file mode 100644 index 00000000000..16669b25333 --- /dev/null +++ b/arch/arm/dts/imx6s-dhcom-drc02-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+) +/* + * Copyright (C) 2022 Philip Oberfichtner <pro@denx.de> + */ + +#include "imx6qdl-dhcom-u-boot.dtsi" + +&fec { + phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/dts/imx6s-dhcom-drc02.dts b/arch/arm/dts/imx6s-dhcom-drc02.dts new file mode 100644 index 00000000000..4077b607c29 --- /dev/null +++ b/arch/arm/dts/imx6s-dhcom-drc02.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 DH electronics GmbH + * + * DHCOM iMX6 variant: + * DHCM-iMX6S-C0800-R102-F0409-E-CAN2-RTC-I-01D2 + * DHCOM PCB number: 493-400 or newer + * DRC02 PCB number: 568-100 or newer + */ +/dts-v1/; + +/* + * The kernel only distinguishes between i.MX6 Quad and DualLite, + * but the Solo is actually a DualLite with only one CPU. So use + * DualLite for the Solo and disable one CPU node. + */ + +#include "imx6dl.dtsi" +#include "imx6qdl-dhcom-som.dtsi" +#include "imx6qdl-dhcom-drc02.dtsi" + +/ { + model = "DH electronics i.MX6S DHCOM on DRC02"; + compatible = "dh,imx6s-dhcom-drc02", "dh,imx6s-dhcom-som", + "fsl,imx6dl"; + + cpus { + /delete-node/ cpu@1; + }; +}; diff --git a/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts b/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts index 154116d01c9..5b022040902 100644 --- a/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts +++ b/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts @@ -392,7 +392,7 @@ &i2c2 { /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ - clock-frequency = <320000>; + clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index 8861542ec58..e9fbf7b8021 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -121,6 +121,10 @@ u-boot,dm-spl; }; +&pinctrl_wdog { + u-boot,dm-spl; +}; + &fec1 { phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 6f70722586d..4d0ecb07d4f 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -80,6 +80,10 @@ u-boot,dm-spl; }; +&pinctrl_wdog { + u-boot,dm-spl; +}; + &gpio1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi new file mode 100644 index 00000000000..ae838caebcf --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2022 Marek Vasut <marex@denx.de> + */ + +#include "imx8mp-u-boot.dtsi" + +/ { + aliases { + eeprom0 = &eeprom0; + eeprom1 = &eeprom1; + mmc0 = &usdhc2; /* MicroSD */ + mmc1 = &usdhc3; /* eMMC */ + mmc2 = &usdhc1; /* SDIO */ + }; + + config { + dh,ram-coding-gpios = <&gpio3 22 0>, <&gpio3 23 0>, <&gpio3 24 0>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; +}; + +&buck4 { + u-boot,dm-spl; +}; + +&buck5 { + u-boot,dm-spl; +}; + +&eqos { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&i2c3 { + u-boot,dm-spl; +}; + +&pinctrl_i2c3 { + u-boot,dm-spl; +}; + +&pinctrl_i2c3_gpio { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&pinctrl_uart1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_200mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3_100mhz { + u-boot,dm-spl; +}; + +&pmic { + u-boot,dm-spl; + + regulators { + u-boot,dm-spl; + }; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&uart1 { + u-boot,dm-spl; +}; + +/* SDIO WiFi */ +&usdhc1 { + status = "disabled"; +}; + +&usdhc2 { + u-boot,dm-spl; +}; + +&usdhc3 { + u-boot,dm-spl; +}; + +&wdog1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2.dts b/arch/arm/dts/imx8mp-dhcom-pdk2.dts new file mode 100644 index 00000000000..e95abfb3e89 --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-pdk2.dts @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2022 Marek Vasut <marex@denx.de> + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/net/qca-ar803x.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include "imx8mp-dhcom-som.dtsi" + +/ { + model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (2)"; + compatible = "dh,imx8mp-dhcom-pdk2", "fsl,imx8mp"; + + chosen { + stdout-path = &uart1; + }; + + gpio-keys { + #size-cells = <0>; + compatible = "gpio-keys"; + + button-0 { + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */ + label = "TA1-GPIO-A"; + linux,code = <KEY_A>; + pinctrl-0 = <&pinctrl_dhcom_a>; + pinctrl-names = "default"; + wakeup-source; + }; + + button-1 { + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */ + label = "TA2-GPIO-B"; + linux,code = <KEY_B>; + pinctrl-0 = <&pinctrl_dhcom_b>; + pinctrl-names = "default"; + wakeup-source; + }; + + button-2 { + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */ + label = "TA3-GPIO-C"; + linux,code = <KEY_C>; + pinctrl-0 = <&pinctrl_dhcom_c>; + pinctrl-names = "default"; + wakeup-source; + }; + + button-3 { + gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* GPIO D */ + label = "TA4-GPIO-D"; + linux,code = <KEY_D>; + pinctrl-0 = <&pinctrl_dhcom_d>; + pinctrl-names = "default"; + wakeup-source; + }; + }; + + led { + compatible = "gpio-leds"; + + led-5 { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* GPIO E */ + pinctrl-0 = <&pinctrl_dhcom_e>; + pinctrl-names = "default"; + }; + + led-6 { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */ + pinctrl-0 = <&pinctrl_dhcom_f>; + pinctrl-names = "default"; + }; + + led-7 { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; /* GPIO H */ + pinctrl-0 = <&pinctrl_dhcom_h>; + pinctrl-names = "default"; + }; + + led-8 { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */ + pinctrl-0 = <&pinctrl_dhcom_i>; + pinctrl-names = "default"; + }; + }; +}; + +/* + * PDK2 carrier board uses SoM with KSZ9131 populated and connected to + * SoM EQoS ethernet RGMII interface. Remove the other SoM PHY DT node. + */ +/delete-node/ ðphy0f; + +/* + * PDK2 carrier board has KSZ9021 PHY populated and connected to SoM FEC + * ethernet RGMII interface. The SoM is not populated with second FEC PHY. + */ +/delete-node/ ðphy1f; + +&fec { /* Second ethernet */ + phy-handle = <ðphypdk>; + + mdio { + ethphypdk: ethernet-phy@7 { /* KSZ 9021 */ + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ethphy1>; + pinctrl-names = "default"; + reg = <7>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + txc-skew-ps = <3000>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + max-speed = <100>; + }; + }; +}; + +&flexcan1 { + status = "okay"; +}; + +&usb3_1 { + fsl,over-current-active-low; +}; diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi b/arch/arm/dts/imx8mp-dhcom-som.dtsi new file mode 100644 index 00000000000..63cc6c92c41 --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi @@ -0,0 +1,1042 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de> + */ + +#include "imx8mp.dtsi" + +/ { + model = "DH electronics i.MX8M Plus DHCOM SoM"; + compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + rtc0 = &rv3032; + rtc1 = &snvs_rtc; + spi0 = &flexspi; + }; + + memory@40000000 { + device_type = "memory"; + /* Memory size 512 MiB..8 GiB will be filled by U-Boot */ + reg = <0x0 0x40000000 0 0x08000000>; + }; + + reg_eth_vio: regulator-eth-vio { + compatible = "regulator-fixed"; + gpio = <&gpio2 10 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_enet_vio>; + pinctrl-names = "default"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "eth_vio"; + vin-supply = <&buck4>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 19 0>; /* SD2_RESET */ + off-on-delay-us = <12000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_3V3_SD"; + startup-delay-us = <100>; + vin-supply = <&buck4>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&eqos { /* First ethernet */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-handle = <ðphy0g>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + /* Up to one of these two PHYs may be populated. */ + ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */ + compatible = "ethernet-phy-id0007.c110", + "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ethphy0>; + pinctrl-names = "default"; + reg = <1>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + /* Non-default PHY population option. */ + status = "disabled"; + }; + + ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */ + compatible = "ethernet-phy-id0022.1642", + "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + pinctrl-0 = <&pinctrl_ethphy0>; + pinctrl-names = "default"; + reg = <5>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + /* Default PHY population option. */ + status = "okay"; + }; + }; +}; + +&fec { /* Second ethernet */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-handle = <ðphy1f>; + phy-mode = "rgmii"; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Up to one PHY may be populated. */ + ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */ + compatible = "ethernet-phy-id0007.c110", + "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ethphy1>; + pinctrl-names = "default"; + reg = <1>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + /* Non-default PHY population option. */ + status = "disabled"; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "disabled"; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash@0 { /* W25Q128JWPIM */ + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&gpio1 { + gpio-line-names = + "DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L", + "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "DHCOM-K", "", "", "", "", + "", "", "", "", "DHCOM-INT", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "SOM-HW0", "", + "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1", + "SOM-MEM2", "SOM-HW2", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "SOM-HW1", "", "", "", "", + "", "", "", "DHCOM-D", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "DHCOM-C", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "DHCOM-E", "DHCOM-F", + "", "", "", "", "", "", "", ""; +}; + +&i2c3 { + /* + * iMX8MP 1P33A Errata ERR007805 + * I2C is limited to 384 kHz due to SoC bug. + */ + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + + /* + * i.MX 8M Plus Data Sheet for Consumer Products + * 3.1.4 Operating ranges + * MIMX8ML8CVNKZAB + */ + regulators { + buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */ + regulator-compatible = "BUCK1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <3125>; + regulator-always-on; + regulator-boot-on; + }; + + buck2: BUCK2 { /* VDD_ARM */ + regulator-compatible = "BUCK2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <3125>; + regulator-always-on; + regulator-boot-on; + }; + + buck4: BUCK4 { /* VDD_3V3 */ + regulator-compatible = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5: BUCK5 { /* VDD_1V8 */ + regulator-compatible = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6: BUCK6 { /* NVCC_DRAM_1V1 */ + regulator-compatible = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1: LDO1 { /* NVCC_SNVS_1V8 */ + regulator-compatible = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3: LDO3 { /* VDDA_1V8 */ + regulator-compatible = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4: LDO4 { /* PMIC_LDO4 */ + regulator-compatible = "LDO4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5: LDO5 { /* NVCC_SD2 */ + regulator-compatible = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + adc@48 { + compatible = "ti,tla2024"; + reg = <0x48>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { /* Voltage over AIN0 and AIN1. */ + reg = <0>; + }; + + channel@1 { /* Voltage over AIN0 and AIN3. */ + reg = <1>; + }; + + channel@2 { /* Voltage over AIN1 and AIN3. */ + reg = <2>; + }; + + channel@3 { /* Voltage over AIN2 and AIN3. */ + reg = <3>; + }; + + channel@4 { /* Voltage over AIN0 and GND. */ + reg = <4>; + }; + + channel@5 { /* Voltage over AIN1 and GND. */ + reg = <5>; + }; + + channel@6 { /* Voltage over AIN2 and GND. */ + reg = <6>; + }; + + channel@7 { /* Voltage over AIN3 and GND. */ + reg = <7>; + }; + }; + + touchscreen@49 { + compatible = "ti,tsc2004"; + reg = <0x49>; + interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + vio-supply = <&buck4>; + }; + + eeprom0: eeprom@50 { /* EEPROM with EQoS MAC address */ + compatible = "atmel,24c02"; + pagesize = <16>; + reg = <0x50>; + }; + + rv3032: rtc@51 { + compatible = "microcrystal,rv3032"; + reg = <0x51>; + interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + }; + + eeprom1: eeprom@53 { /* EEPROM with FEC MAC address */ + compatible = "atmel,24c02"; + pagesize = <16>; + reg = <0x53>; + }; +}; + +&i2c4 { + /* + * iMX8MP 1P33A Errata ERR007805 + * I2C is limited to 384 kHz due to SoC bug. + */ + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c5 { /* HDMI EDID bus */ + /* + * iMX8MP 1P33A Errata ERR007805 + * I2C is limited to 384 kHz due to SoC bug. + */ + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + scl-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pinctrl_pwm1>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&uart1 { + /* CA53 console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + /* Bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_vbus>; + dr_mode = "otg"; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +/* SDIO WiFi */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vmmc-supply = <&buck4>; + bus-width = <4>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { /* muRata 2AE */ + reg = <1>; + compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac"; + /* + * The "host-wake" interrupt output is by default not + * connected to the SoC, but can be connected on to + * SoC pin on the carrier board. + */ + reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; +}; + +/* SD slot */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + vmmc-supply = <&buck4>; + vqmmc-supply = <&buck5>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog_base + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f + &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i + &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l + /* GPIO_M is connected to CLKOUT2 */ + &pinctrl_dhcom_int>; + pinctrl-names = "default"; + + pinctrl_dhcom_a: dhcom-a-grp { + fsl,pins = < + /* ENET_QOS_EVENT0-OUT */ + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x2 + >; + }; + + pinctrl_dhcom_b: dhcom-b-grp { + fsl,pins = < + /* ENET_QOS_EVENT0-IN */ + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x2 + >; + }; + + pinctrl_dhcom_c: dhcom-c-grp { + fsl,pins = < + /* GPIO_C */ + MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x2 + >; + }; + + pinctrl_dhcom_d: dhcom-d-grp { + fsl,pins = < + /* GPIO_D */ + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x2 + >; + }; + + pinctrl_dhcom_e: dhcom-e-grp { + fsl,pins = < + /* GPIO_E */ + MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x2 + >; + }; + + pinctrl_dhcom_f: dhcom-f-grp { + fsl,pins = < + /* GPIO_F */ + MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x2 + >; + }; + + pinctrl_dhcom_g: dhcom-g-grp { + fsl,pins = < + /* GPIO_G */ + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x2 + >; + }; + + pinctrl_dhcom_h: dhcom-h-grp { + fsl,pins = < + /* GPIO_H */ + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x2 + >; + }; + + pinctrl_dhcom_i: dhcom-i-grp { + fsl,pins = < + /* CSI1_SYNC */ + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2 + >; + }; + + pinctrl_dhcom_j: dhcom-j-grp { + fsl,pins = < + /* CSIx_#RST */ + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x2 + >; + }; + + pinctrl_dhcom_k: dhcom-k-grp { + fsl,pins = < + /* CSIx_PWDN */ + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x2 + >; + }; + + pinctrl_dhcom_l: dhcom-l-grp { + fsl,pins = < + /* CSI2_SYNC */ + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x2 + >; + }; + + pinctrl_dhcom_int: dhcom-int-grp { + fsl,pins = < + /* INT_HIGHEST_PRIO */ + MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x2 + >; + }; + + pinctrl_hog_base: dhcom-hog-base-grp { + fsl,pins = < + /* GPIOs for memory coding */ + MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x40000080 + MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x40000080 + MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x40000080 + /* GPIOs for hardware coding */ + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000080 + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000080 + MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x40000080 + >; + }; + + pinctrl_ecspi1: dhcom-ecspi1-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 + >; + }; + + pinctrl_ecspi2: dhcom-ecspi2-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 + >; + }; + + pinctrl_eqos: dhcom-eqos-grp { /* RGMII */ + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + >; + }; + + pinctrl_enet_vio: dhcom-enet-vio-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22 + >; + }; + + pinctrl_ethphy0: dhcom-ethphy0-grp { + fsl,pins = < + /* ENET1_#RST Reset */ + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22 + /* ENET1_#INT Interrupt */ + MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22 + >; + }; + + pinctrl_ethphy1: dhcom-ethphy1-grp { + fsl,pins = < + /* ENET1_#RST Reset */ + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x11 + /* ENET1_#INT Interrupt */ + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x11 + >; + }; + + pinctrl_fec: dhcom-fec-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x1f + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x1f + >; + }; + + pinctrl_flexcan1: dhcom-flexcan1-grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: dhcom-flexcan2-grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154 + MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154 + >; + }; + + pinctrl_flexspi: dhcom-flexspi-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_hdmi: dhcom-hdmi-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154 + >; + }; + + pinctrl_i2c3: dhcom-i2c3-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084 + >; + }; + + pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84 + >; + }; + + pinctrl_i2c4: dhcom-i2c4-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x40000084 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x40000084 + >; + }; + + pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x84 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x84 + >; + }; + + pinctrl_i2c5: dhcom-i2c5-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x40000084 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x40000084 + >; + }; + + pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84 + MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84 + >; + }; + + pinctrl_pmic: dhcom-pmic-grp { + fsl,pins = < + /* PMIC_nINT */ + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090 + >; + }; + + pinctrl_pwm1: dhcom-pwm1-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x6 + >; + }; + + pinctrl_rtc: dhcom-rtc-grp { + fsl,pins = < + /* RTC_#INT Interrupt */ + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x400001c6 + >; + }; + + pinctrl_touch: dhcom-touch-grp { + fsl,pins = < + /* #TOUCH_INT */ + MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x40000080 + >; + }; + + pinctrl_uart1: dhcom-uart1-grp { + fsl,pins = < + /* Console UART */ + MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x49 + MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x49 + MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49 + MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x49 + >; + }; + + pinctrl_uart2: dhcom-uart2-grp { + fsl,pins = < + /* Bluetooth UART */ + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49 + MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49 + >; + }; + + pinctrl_uart3: dhcom-uart3-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x49 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x49 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x49 + >; + }; + + pinctrl_uart4: dhcom-uart4-grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + >; + }; + + pinctrl_usb0_vbus: dhcom-usb0-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0 + >; + }; + + pinctrl_usb1_vbus: dhcom-usb1-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x6 + MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x80 + >; + }; + + pinctrl_usdhc1: dhcom-usdhc1-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + /* BT_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 + /* WL_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 + >; + }; + + pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + /* BT_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 + /* WL_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 + >; + }; + + pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + /* BT_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 + /* WL_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 + >; + }; + + pinctrl_usdhc2: dhcom-usdhc2-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20 + >; + }; + + pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080 + >; + }; + + pinctrl_usdhc3: dhcom-usdhc3-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 + >; + }; + + pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 + >; + }; + + pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 + >; + }; + + pinctrl_wdog: dhcom-wdog-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 7aa908304aa..f43eb6238d0 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -43,6 +43,10 @@ u-boot,dm-spl; }; +&pinctrl_wdog { + u-boot,dm-spl; +}; + &gpio1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mq-cm-u-boot.dtsi b/arch/arm/dts/imx8mq-cm-u-boot.dtsi index 476a8e3dba2..e2f4b0e740d 100644 --- a/arch/arm/dts/imx8mq-cm-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-cm-u-boot.dtsi @@ -9,6 +9,14 @@ }; }; +&pinctrl_uart1 { + u-boot,dm-spl; +}; + +&uart1 { + u-boot,dm-spl; +}; + &binman { u-boot-spl-ddr { filename = "u-boot-spl-ddr.bin"; diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi index 919c1f66d38..67da69a2eb3 100644 --- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi @@ -2,30 +2,6 @@ #include "imx8mq-u-boot.dtsi" -&{/soc@0} { - u-boot,dm-spl; -}; - -&{/soc@0/bus@30000000} { - u-boot,dm-spl; -}; - -&{/soc@0/bus@30400000} { - u-boot,dm-spl; -}; - -&{/soc@0/bus@30800000} { - u-boot,dm-spl; -}; - -&{/soc@0/bus@32c00000} { - u-boot,dm-spl; -}; - -&iomuxc { - u-boot,dm-spl; -}; - &pinctrl_uart1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi index a65a942ee7a..8d6f3058295 100644 --- a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi @@ -5,3 +5,11 @@ ®_usdhc2_vmmc { u-boot,off-on-delay-us = <20000>; }; + +&uart1 { + u-boot,dm-spl; +}; + +&pinctrl_uart1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi b/arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi new file mode 100644 index 00000000000..9537aedf29e --- /dev/null +++ b/arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +&pinctrl_uart1 { + u-boot,dm-spl; +}; + +&uart1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index 1dc060ce0c2..912a3d4a356 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi @@ -10,6 +10,30 @@ }; +&{/soc@0} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30000000} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30400000} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@32c00000} { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + &binman { u-boot-spl-ddr { align = <4>; diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h index 0f1e832c038..2ce8a8f2d41 100644 --- a/arch/arm/include/asm/arch-imx8m/ddr.h +++ b/arch/arm/include/asm/arch-imx8m/ddr.h @@ -723,6 +723,7 @@ void ddrphy_init_read_msg_block(enum fw_type type); void update_umctl2_rank_space_setting(unsigned int pstat_num); void get_trained_CDD(unsigned int fsp); +unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr); static inline void reg32_write(unsigned long addr, u32 val) { diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index b2a8ad77ae1..1da75528d46 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -48,6 +48,16 @@ #ifdef CONFIG_IMX8MM #define USDHC3_BASE_ADDR 0x30B60000 #endif +#define UART_BASE_ADDR(n) ( \ + !!sizeof(struct { \ + static_assert((n) >= 1 && (n) <= 4); \ + int pad; \ + }) * ( \ + (n) == 1 ? UART1_BASE_ADDR : \ + (n) == 2 ? UART2_BASE_ADDR : \ + (n) == 3 ? UART3_BASE_ADDR : \ + UART4_BASE_ADDR) \ + ) #define TZASC_BASE_ADDR 0x32F80000 diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h b/arch/arm/include/asm/arch-imx8ulp/s400_api.h index 1856659877e..b3e6b3fa45d 100644 --- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h +++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h @@ -17,6 +17,7 @@ #define AHAB_WRITE_SECURE_FUSE_REQ_CID 0x91 #define AHAB_FWD_LIFECYCLE_UP_REQ_CID 0x95 #define AHAB_READ_FUSE_REQ_CID 0x97 +#define AHAB_GET_FW_VERSION_CID 0x9D #define AHAB_RELEASE_RDC_REQ_CID 0xC4 #define AHAB_WRITE_FUSE_REQ_CID 0xD6 #define AHAB_CAAM_RELEASE_CID 0xD7 @@ -39,6 +40,7 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response); int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response); int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response); int ahab_release_caam(u32 core_did, u32 *response); +int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response); int ahab_dump_buffer(u32 *buffer, u32 buffer_length); #endif diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index d39f6b03508..77794d7d03d 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -179,16 +179,16 @@ struct fuse_bank0_regs { #define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) #define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) #define IMX_RTC_BASE (0x07000 + IMX_IO_BASE) -#define UART1_BASE (0x0a000 + IMX_IO_BASE) -#define UART2_BASE (0x0b000 + IMX_IO_BASE) -#define UART3_BASE (0x0c000 + IMX_IO_BASE) -#define UART4_BASE (0x0d000 + IMX_IO_BASE) +#define UART1_BASE_ADDR (0x0a000 + IMX_IO_BASE) +#define UART2_BASE_ADDR (0x0b000 + IMX_IO_BASE) +#define UART3_BASE_ADDR (0x0c000 + IMX_IO_BASE) +#define UART4_BASE_ADDR (0x0d000 + IMX_IO_BASE) #define I2C1_BASE_ADDR (0x12000 + IMX_IO_BASE) #define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) #define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) #define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE) -#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE) -#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE) +#define UART5_BASE_ADDR (0x1b000 + IMX_IO_BASE) +#define UART6_BASE_ADDR (0x1c000 + IMX_IO_BASE) #define I2C2_BASE_ADDR (0x1D000 + IMX_IO_BASE) #define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE) #define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) @@ -204,6 +204,18 @@ struct fuse_bank0_regs { #define NFC_BASE_ADDR IMX_NFC_BASE +#define UART_BASE_ADDR(n) ( \ + !!sizeof(struct { \ + static_assert((n) >= 1 && (n) <= 6); \ + int pad; \ + }) * ( \ + (n) == 1 ? UART1_BASE_ADDR : \ + (n) == 2 ? UART2_BASE_ADDR : \ + (n) == 3 ? UART3_BASE_ADDR : \ + (n) == 4 ? UART4_BASE_ADDR : \ + (n) == 5 ? UART5_BASE_ADDR : \ + UART6_BASE_ADDR) \ + ) /* FMCR System Control bit definition*/ #define UART4_RXD_CTL (1 << 25) diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 566db549ec6..d5c0ed8e6c2 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -598,6 +598,18 @@ struct esdc_regs { #define UART4_BASE 0x43FB0000 #define UART5_BASE 0x43FB4000 +#define UART_BASE_ADDR(n) ( \ + !!sizeof(struct { \ + static_assert((n) >= 1 && (n) <= 5); \ + int pad; \ + }) * ( \ + (n) == 1 ? UART1_BASE : \ + (n) == 2 ? UART2_BASE : \ + (n) == 3 ? UART3_BASE : \ + (n) == 4 ? UART4_BASE : \ + UART5_BASE_ADDR) \ + ) + #define I2C1_BASE_ADDR 0x43f80000 #define I2C1_CLK_OFFSET 26 #define I2C2_BASE_ADDR 0x43F98000 diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c index f119e9f88d5..c54f52b343c 100644 --- a/arch/arm/mach-imx/cmd_nandbcb.c +++ b/arch/arm/mach-imx/cmd_nandbcb.c @@ -506,10 +506,6 @@ static int read_fcb(struct boot_config *boot_cfg, struct fcb_block *fcb, int ret = 0; mtd = boot_cfg->mtd; - if (mtd_block_isbad(mtd, off)) { - printf("Block %d is bad, skipped\n", (int)CONV_TO_BLOCKS(off)); - return 1; - } fcb_raw_page = kzalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL); if (!fcb_raw_page) { @@ -530,7 +526,7 @@ static int read_fcb(struct boot_config *boot_cfg, struct fcb_block *fcb, else if (plat_config.misc_flags & FCB_ENCODE_BCH_40b) mxs_nand_mode_fcb_40bit(mtd); - ret = nand_read(mtd, off, &size, (u_char *)fcb); + ret = nand_read_skip_bad(mtd, off, &size, NULL, mtd->size, (u_char *)fcb); /* switch BCH back */ mxs_nand_mode_normal(mtd); @@ -617,6 +613,7 @@ static int write_fcb(struct boot_config *boot_cfg, struct fcb_block *fcb) for (i = 0; i < g_boot_search_count; i++) { if (mtd_block_isbad(mtd, off)) { printf("Block %d is bad, skipped\n", i); + off += mtd->erasesize; continue; } @@ -676,20 +673,15 @@ static int read_dbbt(struct boot_config *boot_cfg, struct dbbt_block *dbbt, void *dbbt_data_page, loff_t off) { size_t size; + size_t actual_size; struct mtd_info *mtd; loff_t to; int ret; mtd = boot_cfg->mtd; - if (mtd_block_isbad(mtd, off)) { - printf("Block %d is bad, skipped\n", - (int)CONV_TO_BLOCKS(off)); - return 1; - } - size = sizeof(struct dbbt_block); - ret = nand_read(mtd, off, &size, (u_char *)dbbt); + ret = nand_read_skip_bad(mtd, off, &size, &actual_size, mtd->size, (u_char *)dbbt); printf("NAND DBBT read from 0x%llx offset 0x%zx read: %s\n", off, size, ret ? "ERROR" : "OK"); if (ret) @@ -697,9 +689,9 @@ static int read_dbbt(struct boot_config *boot_cfg, struct dbbt_block *dbbt, /* dbbtpages == 0 if no bad blocks */ if (dbbt->dbbtpages > 0) { - to = off + 4 * mtd->writesize; + to = off + 4 * mtd->writesize + actual_size - size; size = mtd->writesize; - ret = nand_read(mtd, to, &size, dbbt_data_page); + ret = nand_read_skip_bad(mtd, to, &size, NULL, mtd->size, dbbt_data_page); printf("DBBT data read from 0x%llx offset 0x%zx read: %s\n", to, size, ret ? "ERROR" : "OK"); @@ -729,6 +721,7 @@ static int write_dbbt(struct boot_config *boot_cfg, struct dbbt_block *dbbt, if (mtd_block_isbad(mtd, off)) { printf("Block %d is bad, skipped\n", (int)(i + CONV_TO_BLOCKS(off))); + off += mtd->erasesize; continue; } diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 0858ea5f057..936c8f865aa 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -100,7 +100,7 @@ int arch_misc_init(void) ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); if (ret) - printf("Failed to initialize %s: %d\n", dev->name, ret); + printf("Failed to initialize caam_jr: %d\n", ret); } return 0; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 24299ae037f..61397bf88d1 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -148,6 +148,13 @@ config TARGET_IMX8MN_VENICE select GATEWORKS_SC select MISC +config TARGET_IMX8MP_DH_DHCOM_PDK2 + bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus" + select BINMAN + select IMX8MP + select IMX8M_LPDDR4 + select SUPPORT_SPL + config TARGET_IMX8MP_EVK bool "imx8mp LPDDR4 EVK board" select BINMAN @@ -265,6 +272,7 @@ source "board/beacon/imx8mn/Kconfig" source "board/bsh/imx8mn_smm_s2/Kconfig" source "board/compulab/imx8mm-cl-iot-gate/Kconfig" source "board/data_modul/imx8mm_edm_sbc/Kconfig" +source "board/dhelectronics/dh_imx8mp/Kconfig" source "board/engicam/imx8mm/Kconfig" source "board/freescale/imx8mq_evk/Kconfig" source "board/freescale/imx8mm_evk/Kconfig" diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 8e23e6da326..59335356b57 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -72,15 +72,13 @@ void enable_tzc380(void) * According to TRM, TZASC_ID_SWAP_BYPASS should be set in * order to avoid AXI Bus errors when GPU is in use */ - if (is_imx8mq() || is_imx8mm() || is_imx8mn() || is_imx8mp()) - setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS); + setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS); /* * imx8mn and imx8mp implements the lock bit for * TZASC_ID_SWAP_BYPASS, enable it to lock settings */ - if (is_imx8mn() || is_imx8mp()) - setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK); + setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK); /* * set Region 0 attribute to allow secure and non-secure @@ -1410,7 +1408,7 @@ int arch_misc_init(void) ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); if (ret) - printf("Failed to initialize %s: %d\n", dev->name, ret); + printf("Failed to initialize caam_jr: %d\n", ret); } return 0; @@ -1535,6 +1533,16 @@ enum env_location arch_env_get_location(enum env_operation op, int prio) return ENVL_UNKNOWN; switch (dev) { + case USB_BOOT: + if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) + return ENVL_SPI_FLASH; + if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND)) + return ENVL_NAND; + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + return ENVL_MMC; + if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) + return ENVL_NOWHERE; + return ENVL_UNKNOWN; case QSPI_BOOT: case SPI_NOR_BOOT: if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) @@ -1563,3 +1571,29 @@ enum env_location arch_env_get_location(enum env_operation op, int prio) } #endif + +#ifdef CONFIG_IMX_BOOTAUX +const struct rproc_att hostmap[] = { + /* aux core , host core, size */ + { 0x00000000, 0x007e0000, 0x00020000 }, + /* OCRAM_S */ + { 0x00180000, 0x00180000, 0x00008000 }, + /* OCRAM */ + { 0x00900000, 0x00900000, 0x00020000 }, + /* OCRAM */ + { 0x00920000, 0x00920000, 0x00020000 }, + /* QSPI Code - alias */ + { 0x08000000, 0x08000000, 0x08000000 }, + /* DDR (Code) - alias */ + { 0x10000000, 0x80000000, 0x0FFE0000 }, + /* TCML */ + { 0x1FFE0000, 0x007E0000, 0x00040000 }, + /* OCRAM_S */ + { 0x20180000, 0x00180000, 0x00008000 }, + /* OCRAM */ + { 0x20200000, 0x00900000, 0x00040000 }, + /* DDR (Data) */ + { 0x40000000, 0x40000000, 0x80000000 }, + { /* sentinel */ } +}; +#endif diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index 9ffe5ac6e34..8115bf40f1a 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -14,7 +14,13 @@ #include <linux/compiler.h> #include <cpu_func.h> -#ifndef CONFIG_IMX8M +/* Just to avoid build error */ +#if CONFIG_IS_ENABLED(IMX8M) +#define SRC_M4C_NON_SCLR_RST_MASK BIT(0) +#define SRC_M4_ENABLE_MASK BIT(0) +#define SRC_M4_REG_OFFSET 0 +#endif + const __weak struct rproc_att hostmap[] = { }; static const struct rproc_att *get_host_mapping(unsigned long auxcore) @@ -36,10 +42,11 @@ static const struct rproc_att *get_host_mapping(unsigned long auxcore) * is valid, returns the entry point address. * Translates load addresses in the elf file to the U-Boot address space. */ -static unsigned long load_elf_image_m_core_phdr(unsigned long addr) +static unsigned long load_elf_image_m_core_phdr(unsigned long addr, ulong *stack) { Elf32_Ehdr *ehdr; /* ELF header structure pointer */ Elf32_Phdr *phdr; /* Program header structure pointer */ + int num = 0; int i; ehdr = (Elf32_Ehdr *)addr; @@ -54,19 +61,24 @@ static unsigned long load_elf_image_m_core_phdr(unsigned long addr) continue; if (!mmap) { - printf("Invalid aux core address: %08x", + printf("Invalid aux core address: %08x\n", phdr->p_paddr); return 0; } - dst = (void *)(phdr->p_paddr - mmap->da) + mmap->sa; + dst = (void *)(ulong)(phdr->p_paddr - mmap->da) + mmap->sa; src = (void *)addr + phdr->p_offset; debug("Loading phdr %i to 0x%p (%i bytes)\n", i, dst, phdr->p_filesz); - if (phdr->p_filesz) + if (phdr->p_filesz) { memcpy(dst, src, phdr->p_filesz); + /* Stack in __isr_vector is the first section/word */ + if (!num) + *stack = *(uint32_t *)src; + num++; + } if (phdr->p_filesz != phdr->p_memsz) memset(dst + phdr->p_filesz, 0x00, phdr->p_memsz - phdr->p_filesz); @@ -77,7 +89,6 @@ static unsigned long load_elf_image_m_core_phdr(unsigned long addr) return ehdr->e_entry; } -#endif int arch_auxiliary_core_up(u32 core_id, ulong addr) { @@ -86,20 +97,17 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) if (!addr) return -EINVAL; -#ifdef CONFIG_IMX8M - stack = *(u32 *)addr; - pc = *(u32 *)(addr + 4); -#else /* * handling ELF64 binaries * isn't supported yet. */ if (valid_elf_image(addr)) { - stack = 0x0; - pc = load_elf_image_m_core_phdr(addr); + pc = load_elf_image_m_core_phdr(addr, &stack); if (!pc) return CMD_RET_FAILURE; + if (!CONFIG_IS_ENABLED(ARM64)) + stack = 0x0; } else { /* * Assume binary file with vector table at the beginning. @@ -109,7 +117,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) stack = *(u32 *)addr; pc = *(u32 *)(addr + 4); } -#endif + printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n", stack, pc); @@ -120,36 +128,32 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) flush_dcache_all(); /* Enable M4 */ -#ifdef CONFIG_IMX8M - arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, - 0, 0, 0, 0, NULL); -#else - clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, - SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK); -#endif + if (CONFIG_IS_ENABLED(IMX8M)) { + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0, 0, 0, 0, NULL); + } else { + clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, + SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK); + } return 0; } int arch_auxiliary_core_check_up(u32 core_id) { -#ifdef CONFIG_IMX8M struct arm_smccc_res res; - - arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, - 0, 0, 0, 0, &res); - - return res.a0; -#else unsigned int val; + if (CONFIG_IS_ENABLED(IMX8M)) { + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0, 0, 0, 0, &res); + return res.a0; + } + val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET); if (val & SRC_M4C_NON_SCLR_RST_MASK) return 0; /* assert in reset */ return 1; -#endif } /* diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 947b73fab29..eceb730856f 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -347,6 +347,20 @@ config TARGET_MX6Q_ENGICAM select SUPPORT_SPL imply CMD_DM +config TARGET_MX6Q_ACC + bool "Support for Bosch ACC board" + depends on MX6QDL + select BOARD_LATE_INIT + select OF_CONTROL + select SPL_OF_LIBFDT + select DM + select DM_ETH + select DM_GPIO + select DM_I2C + select DM_MMC + select DM_THERMAL + select SUPPORT_SPL + config TARGET_MX6SABREAUTO bool "mx6sabreauto" depends on MX6QDL @@ -686,6 +700,7 @@ source "board/freescale/mx6sxsabresd/Kconfig" source "board/freescale/mx6sxsabreauto/Kconfig" source "board/freescale/mx6ul_14x14_evk/Kconfig" source "board/freescale/mx6ullevk/Kconfig" +source "board/bosch/acc/Kconfig" source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" source "board/phytec/pcl063/Kconfig" diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 2434bcfa987..67bd9919892 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -744,7 +744,7 @@ int arch_misc_init(void) ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); if (ret) - printf("Failed to initialize %s: %d\n", dev->name, ret); + printf("Failed to initialize caam_jr: %d\n", ret); } setup_serial_number(); return 0; diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index dc9ac31eb0f..c672be5d5dd 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -361,7 +361,7 @@ int arch_misc_init(void) int ret; ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); if (ret) - printf("Failed to initialize %s: %d\n", dev->name, ret); + printf("Failed to initialize caam_jr: %d\n", ret); } return 0; diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 08bdc0c4af5..217b7c45867 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -93,7 +93,7 @@ int arch_misc_init(void) ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); if (ret) - printf("Failed to initialize %s: %d\n", dev->name, ret); + printf("Failed to initialize caam_jr: %d\n", ret); } return 0; |