diff options
| author | Jernej Skrabec <jernej.skrabec@gmail.com> | 2022-01-29 16:58:43 +0100 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2022-01-30 01:25:00 +0000 |
| commit | e97943b732d0e0588cfab3a8cb53459ca14dc81d (patch) | |
| tree | e211e21e8b71925f689df84fc76678fa5f3bfa1f /arch/arm/mach-sunxi | |
| parent | 18a59276983903ea4364d2945c880a62392e4e34 (diff) | |
sunxi: Fix H616 DRAM read calibration for dual rank
Although it isn't known what bit 0 in PHY reg 8 does, it's obvious that
it has to be set before read calibration and cleared afterwards. This is
already done for first rank, but not for second (copy & paste error.)
Fix it.
Fixes: f4317dbd06b6 ("sunxi: Add H616 DRAM support")
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'arch/arm/mach-sunxi')
| -rw-r--r-- | arch/arm/mach-sunxi/dram_sun50i_h616.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 76f520f4e7..83e8abc2f8 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -360,7 +360,7 @@ static bool mctl_phy_read_calibration(struct dram_para *para) } } - setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1); } clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30); |