diff options
| author | Patrick Delaunay <patrick.delaunay@st.com> | 2019-02-27 17:01:26 +0100 |
|---|---|---|
| committer | Patrick Delaunay <patrick.delaunay@st.com> | 2019-04-12 16:09:13 +0200 |
| commit | 59a54e37a6adb86c920d8cadbac663e8fb2eeb2c (patch) | |
| tree | 141cf8d2dba5c8abe4fa71e350c1c8a95245a9d7 /arch/arm/mach-stm32mp | |
| parent | 8983ba2751ec008e13583960d711ec010e109fe6 (diff) | |
stm32mp1: basic boot: SPL enable access to GPIOZ bank
SPL need to set GPIOZ_SECCFGR = 0 to enable access to GPIOZ bank
(open security).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'arch/arm/mach-stm32mp')
| -rw-r--r-- | arch/arm/mach-stm32mp/cpu.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 5d79bde733..f39941edfc 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -18,6 +18,7 @@ #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) #define RCC_BDCR (STM32_RCC_BASE + 0x0140) #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) +#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210) #define RCC_BDCR_VSWRST BIT(31) #define RCC_BDCR_RTCSRC GENMASK(17, 16) #define RCC_DBGCFGR_DBGCKEN BIT(8) @@ -44,6 +45,9 @@ #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) #define DBGMCU_IDC_REV_ID_SHIFT 16 +/* GPIOZ registers */ +#define GPIOZ_SECCFGR 0x54004030 + /* boot interface from Bootrom * - boot instance = bit 31:16 * - boot device = bit 15:0 @@ -135,6 +139,10 @@ static void security_init(void) * Bit 16 ITAMP1E: RTC power domain supply monitoring */ writel(0x0, TAMP_CR1); + + /* GPIOZ: deactivate the security */ + writel(BIT(0), RCC_MP_AHB5ENSETR); + writel(0x0, GPIOZ_SECCFGR); } #endif /* CONFIG_STM32MP1_TRUSTED */ |