diff options
author | Vikas Manocha <vikas.manocha@st.com> | 2016-03-09 15:18:13 -0800 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2016-03-26 18:49:28 -0400 |
commit | 9ecb0c416c68d3105bc9b6607bc8601cab2ecf35 (patch) | |
tree | 049e372d9109963019def79dceebaf24d8713c2e /arch/arm/mach-stm32 | |
parent | f9d0fd8a566f78f27a510258c34b3526f9822e92 (diff) |
stm32: stm32f4: move flash driver to mtd driver location
Same flash driver can be used by other stm32 families like stm32f7.
Better place for this driver would be mtd driver location.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Diffstat (limited to 'arch/arm/mach-stm32')
-rw-r--r-- | arch/arm/mach-stm32/stm32f4/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/mach-stm32/stm32f4/clock.c | 10 | ||||
-rw-r--r-- | arch/arm/mach-stm32/stm32f4/flash.c | 146 |
3 files changed, 2 insertions, 156 deletions
diff --git a/arch/arm/mach-stm32/stm32f4/Makefile b/arch/arm/mach-stm32/stm32f4/Makefile index 42d01db14d6..020e78370c8 100644 --- a/arch/arm/mach-stm32/stm32f4/Makefile +++ b/arch/arm/mach-stm32/stm32f4/Makefile @@ -8,4 +8,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += soc.o clock.o timer.o flash.o +obj-y += soc.o clock.o timer.o diff --git a/arch/arm/mach-stm32/stm32f4/clock.c b/arch/arm/mach-stm32/stm32f4/clock.c index 631f36a5a16..15fcadbbe6f 100644 --- a/arch/arm/mach-stm32/stm32f4/clock.c +++ b/arch/arm/mach-stm32/stm32f4/clock.c @@ -66,11 +66,6 @@ #define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1) #define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0) -#define FLASH_ACR_WS(n) n -#define FLASH_ACR_PRFTEN (1 << 8) -#define FLASH_ACR_ICEN (1 << 9) -#define FLASH_ACR_DCEN (1 << 10) - /* * RCC GPIO specific definitions */ @@ -181,10 +176,7 @@ int configure_clocks(void) while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY)) ; - /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */ - writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN - | FLASH_ACR_DCEN, &STM32_FLASH->acr); - + stm32_flash_latency_cfg(5); clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL); diff --git a/arch/arm/mach-stm32/stm32f4/flash.c b/arch/arm/mach-stm32/stm32f4/flash.c deleted file mode 100644 index a379f477df5..00000000000 --- a/arch/arm/mach-stm32/stm32f4/flash.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/stm32.h> - -#define STM32_FLASH_KEY1 0x45670123 -#define STM32_FLASH_KEY2 0xCDEF89AB - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { - [0 ... 3] = 16 * 1024, - [4] = 64 * 1024, - [5 ... 11] = 128 * 1024 -}; - -static void stm32f4_flash_lock(u8 lock) -{ - if (lock) { - setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_LOCK); - } else { - writel(STM32_FLASH_KEY1, &STM32_FLASH->key); - writel(STM32_FLASH_KEY2, &STM32_FLASH->key); - } -} - -unsigned long flash_init(void) -{ - unsigned long total_size = 0; - u8 i, j; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - flash_info[i].flash_id = FLASH_STM32F4; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 20); - flash_info[i].size = sect_sz_kb[0]; - for (j = 1; j < CONFIG_SYS_MAX_FLASH_SECT; j++) { - flash_info[i].start[j] = flash_info[i].start[j - 1] - + (sect_sz_kb[j - 1]); - flash_info[i].size += sect_sz_kb[j]; - } - total_size += flash_info[i].size; - } - - return total_size; -} - -void flash_print_info(flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } else if (info->flash_id == FLASH_STM32F4) { - printf("STM32F4 Embedded Flash\n"); - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf("\n"); - return; -} - -int flash_erase(flash_info_t *info, int first, int last) -{ - u8 bank = 0xFF; - int i; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - if (info == &flash_info[i]) { - bank = i; - break; - } - } - if (bank == 0xFF) - return -1; - - stm32f4_flash_lock(0); - - for (i = first; i <= last; i++) { - while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY) - ; - - /* clear old sector number before writing a new one */ - clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SNB_MASK); - - if (bank == 0) { - setbits_le32(&STM32_FLASH->cr, - (i << STM32_FLASH_CR_SNB_OFFSET)); - } else if (bank == 1) { - setbits_le32(&STM32_FLASH->cr, - ((0x10 | i) << STM32_FLASH_CR_SNB_OFFSET)); - } else { - stm32f4_flash_lock(1); - return -1; - } - setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER); - setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_STRT); - - while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY) - ; - - clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER); - } - - stm32f4_flash_lock(1); - return 0; -} - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong i; - - while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY) - ; - - stm32f4_flash_lock(0); - - setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG); - /* To make things simple use byte writes only */ - for (i = 0; i < cnt; i++) { - *(uchar *)(addr + i) = src[i]; - while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY) - ; - } - clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG); - stm32f4_flash_lock(1); - - return 0; -} |