diff options
| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2017-12-28 15:09:02 +0300 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2018-01-26 11:25:49 +0530 |
| commit | 21143ce127b953356bd6174fb4e4892af3a92d0f (patch) | |
| tree | ffd3b5a5ad4e5e0ff73761ae8c86321ff28a1e61 /arch/arm/mach-socfpga | |
| parent | aaa21d3ffc023623a3a8247e5fa25d0db2bfb630 (diff) | |
SOCFPGA: clock manager: implement dw_spi_get_clk function
Implement dw_spi_get_clk function to override its weak
implementation in designware_spi.c driver.
We need this change to get rid of cm_get_spi_controller_clk_hz
function and clock_manager.h include in designware_spi.c driver.
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'arch/arm/mach-socfpga')
| -rw-r--r-- | arch/arm/mach-socfpga/clock_manager_arria10.c | 9 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/clock_manager_gen5.c | 9 |
2 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c index 482b8543f4..623a266f80 100644 --- a/arch/arm/mach-socfpga/clock_manager_arria10.c +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -7,6 +7,7 @@ #include <common.h> #include <fdtdec.h> #include <asm/io.h> +#include <dm.h> #include <asm/arch/clock_manager.h> DECLARE_GLOBAL_DATA_PTR; @@ -1076,6 +1077,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void) return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB); } +/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */ +int dw_spi_get_clk(struct udevice *bus, ulong *rate) +{ + *rate = cm_get_spi_controller_clk_hz(); + + return 0; +} + void cm_print_clock_quick_summary(void) { printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c index a23f3fc5d0..3d048ba3e4 100644 --- a/arch/arm/mach-socfpga/clock_manager_gen5.c +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c @@ -6,6 +6,7 @@ #include <common.h> #include <asm/io.h> +#include <dm.h> #include <asm/arch/clock_manager.h> #include <wait_bit.h> @@ -507,6 +508,14 @@ unsigned int cm_get_spi_controller_clk_hz(void) return clock; } +/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */ +int dw_spi_get_clk(struct udevice *bus, ulong *rate) +{ + *rate = cm_get_spi_controller_clk_hz(); + + return 0; +} + void cm_print_clock_quick_summary(void) { printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); |