diff options
| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2019-11-27 15:55:16 +0800 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2020-01-07 14:38:33 +0100 |
| commit | fd5374aa29cc00d5694b47256c0a7c820e3d0892 (patch) | |
| tree | f7722a3fcd9e0a1bb90b630837f207c12f5d1eb7 /arch/arm/mach-socfpga/reset_manager_s10.c | |
| parent | 8b7962a34923d8eaa2459376b12f8cead7f3894a (diff) | |
arm: socfpga: Move Stratix10 and Agilex reset manager common code
Move Stratix10 and Agilex reset manager common code to
reset_manager_soc64.h. Changed macros to RSTMGR_SOC64_*.
Remove unused RSTMGR_XXX defines.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch/arm/mach-socfpga/reset_manager_s10.c')
| -rw-r--r-- | arch/arm/mach-socfpga/reset_manager_s10.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index e92de3d84e..f449cb67d7 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -18,13 +18,13 @@ void socfpga_per_reset(u32 reset, int set) unsigned long reg; if (RSTMGR_BANK(reset) == 0) - reg = RSTMGR_S10_MPUMODRST; + reg = RSTMGR_SOC64_MPUMODRST; else if (RSTMGR_BANK(reset) == 1) - reg = RSTMGR_S10_PER0MODRST; + reg = RSTMGR_SOC64_PER0MODRST; else if (RSTMGR_BANK(reset) == 2) - reg = RSTMGR_S10_PER1MODRST; + reg = RSTMGR_SOC64_PER1MODRST; else if (RSTMGR_BANK(reset) == 3) - reg = RSTMGR_S10_BRGMODRST; + reg = RSTMGR_SOC64_BRGMODRST; else /* Invalid reset register, do nothing */ return; @@ -47,9 +47,9 @@ void socfpga_per_reset_all(void) /* disable all except OCP and l4wd0. OCP disable later */ writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK), - socfpga_get_rstmgr_addr() + RSTMGR_S10_PER0MODRST); - writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_S10_PER0MODRST); - writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_S10_PER1MODRST); + socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST); + writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST); + writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST); } void socfpga_bridges_reset(int enable) @@ -60,7 +60,7 @@ void socfpga_bridges_reset(int enable) SYSMGR_S10_NOC_IDLEREQ_CLR, ~0); /* Release all bridges from reset state */ - clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_S10_BRGMODRST, + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, ~0); /* Poll until all idleack to 0 */ @@ -86,7 +86,7 @@ void socfpga_bridges_reset(int enable) ; /* Reset all bridges (except NOR DDR scheduler & F2S) */ - setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_S10_BRGMODRST, + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, ~(RSTMGR_BRGMODRST_DDRSCH_MASK | RSTMGR_BRGMODRST_FPGA2SOC_MASK)); @@ -100,6 +100,6 @@ void socfpga_bridges_reset(int enable) */ int cpu_has_been_warmreset(void) { - return readl(socfpga_get_rstmgr_addr() + RSTMGR_S10_STATUS) & + return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) & RSTMGR_L4WD_MPU_WARMRESET_MASK; } |